AT25SF641B datasheet(31/59 Pages) DIALOG

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AT25SF641B

DS-AT25SF641B–191D–12-2020

9.5

Enable Reset (66h) and Reset Device (99h)

Because of the small package and the limitation on the number of pins, the AT25SF641B provides a software

Reset instruction instead of a dedicated RESET pin. Once the software Reset instruction is accepted, any on-going

internal operations are terminated, and the device returns to its default power-on state and loses all the current

volatile settings, including the Volatile Status Register bits, Write Enable Latch (WEL) status, Program/Erase

Suspend status, Continuous Read Mode bit setting (M7-M0), and Wrap Bit setting (W6-W4).

To avoid accidental reset, the Enable Reset and Reset Device instructions must be issued in sequence. Any other

commands other than Reset (99h) after the Enable Reset (66h) command disables the Reset Enable state. A new

sequence of Enable Reset and Reset Device is needed to reset the device. Once the Reset command is accepted

by the device, the device takes approximately 30 µs to reset. During this period, no command is accepted.

The Enable Reset and Reset Device instruction sequence are shown in Figure 9-3.

Data corruption can happen if there is an on-going or suspended internal Erase or Program operation when the

Reset command sequence is accepted by the device. Check the BUSY bit and the SUS bit in the Status Register

before issuing the Reset command sequence.

Figure 9-3. Enable Reset (66h) and Reset Device (99h) Command Timing (SPI Mode)

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