ADP5350ACBZ-1-R7 datasheet(56/63 Pages) AD

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ADP5350

Data Sheet

Rev. B | Page 56 of 63

Bit No.

Mnemonic

Access

Default

Description

PG4_BST_MASK

R/W

This bit configures the external PGOOD pin. This bit is only effective in boost

standalone fixed output mode.

0 = do not output the boost PGOOD signal to the external PGOOD pin.

1 = output the boost PGOOD signal to the external PGOOD pin.

PG1_LDO1_MASK1

R/W

Factory

setting

This bit configures the external PGOOD pin. This bit is not effective if the LDO

regulator is configured as a load switch mode.

0 = do not output the LDO1 PGOOD signal to the external PGOOD pin.

1 = output the LDO1 PGOOD signal to the external PGOOD pin.

When the PGOOD pin is selected for PG1_LDO1_MASK, the ADP5350 quiescent current increases to 4 µA typically.

Table 75. CHARGER_INTERRUPT_ENABLE, Register Address 0x38 Bit Descriptions

Bit No.

Mnemonic

Access

Default

Description

EN_IND_PEAK_INT

R/W

When high, the inductor peak current-limit interrupt is enabled.

EN_THERM_LIM_INT

R/W

When high, the isothermal charging interrupt is allowed.

EN_WD_INT

R/W

When high, the watchdog alarm interrupt is allowed.

EN_TSD_INT

R/W

When high, the overtemperature 130°C warning interrupt is allowed.

EN_THR_INT

R/W

When high, the THR temperature thresholds interrupt is allowed.

EN_BAT_INT

R/W

When high, the battery voltage thresholds interrupt is allowed.

EN_CHG_INT

R/W

When high, the charger mode change interrupt is allowed.

EN_VIN_INT

R/W

When high, the VBUSx pin voltage thresholds interrupt is allowed.

Table 76. CHARGER_INTERRUPT_FLAG, Register Address 0x39 Bit Descriptions

Bit No.

Mnemonic

Access

Default

Description

IND_PEAK_INT1

When high, this bit indicates an interrupt caused by an inductor peak current limit.

THERM_LIM_INT1

When high, this bit indicates an interrupt caused by isothermal charging.

WD_INT1

When high, this bit indicates an interrupt caused by the watchdog alarm. The watchdog

timer expires within 2 sec or 4 sec depending on the tWD setting of 32 sec or 64 sec,

respectively.

TSD_INT1

When high, this bit indicates an interrupt caused by an overtemperature fault.

THR_INT1

When high, this bit indicates an interrupt caused by THR temperature thresholds.

BAT_INT1

When high, this bit indicates an interrupt caused by battery voltage thresholds.

CHG_INT1

When high, this bit indicates an interrupt caused by a charger mode change.

VIN_INT1

When high, this bit indicates an interrupt caused by VBUSx voltage thresholds.

These bits reset to 0 automatically when read.

Table 77. BOOST_LDO_INTERRUPT_ENABLE, Register Address 0x3A Bit Descriptions

Bit No.

Mnemonic

Access

Default

Description

[7:3]

Not used

Not used.

EN_LED_OPEN_INT

R/W

0 = LED open events does not trigger the interrupt pin.

1 = LED open events triggers the interrupt pin.

EN_PG4_BST_INT

R/W

0 = power-good warning on the boost regulator does not trigger the

interrupt pin.

1 = power-good warning on the boost regulator triggers the

interrupt pin.

EN_PG1_LDO1_INT

R/W

0 = power-good warning on LDO1 does not trigger the interrupt pin.

1 = power-good warning on LDO1 triggers the interrupt pin.

ADP5350ACBZ-1-R7 Datenblatt(PDF) 56 Page - Analog Devices

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