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ADP5350ACPZ-1-R7 Datenblatt(PDF) 43 Page - Analog Devices

Teilenummer ADP5350ACPZ-1-R7
Bauteilbeschribung  Advanced Battery Management PMIC with Inductive Boost LED and Three LDO Regulators
PDF  63 Pages
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Hersteller  AD [Analog Devices]
Direct Link  http://www.analog.com
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ADP5350ACPZ-1-R7 Datenblatt(HTML) 43 Page - Analog Devices

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Data Sheet
ADP5350
Rev. B | Page 43 of 63
Bit No.
Mnemonic
Access
Default
Description
[2:0]
CHAGER_STATUS[2:0]
R
Not applicable
Charger status bus.
000 = off.
001 = trickle charge.
010 = fast charge (CC mode).
011 = fast charge (CV mode).
100 = charge complete.
101 = suspend.
110 = trickle, fast, or safety charge timer expired.
111 = battery detection.
Table 28. CHARGER_STATUS2, Register Address 0x09 Bit Descriptions
Bit No.
Mnemonic
Access
Default
Description
[7:5]
THR_STATUS[2:0]
R
Not applicable
THR pin status.
000 = off.
001 = battery cold.
010 = battery cool.
011 = battery warm.
100 = battery hot.
111 = thermistor is in normal operating temperature, between
the battery cool and battery warm settings.
4
IPK_STAT
R
Not applicable
Peak current limit status bit. Set high if four or more peak
inductor current limits are reached in succession.
3
Not used
R
Not used.
[2:0]
BATTERY_STATUS[2:0]
R
Not applicable
Battery status bus.
000 = battery monitor off.
001 = no battery.
010 = VBSNS < VTRK.
011 = VTRK ≤ VBSNS < VWEAK.
100 = VBSNS ≥ VWEAK.
Table 29. CHARGER_FAULT, Register Address 0x0A Bit Descriptions1
Bit No.
Mnemonic
Access
Default
Description
[7:4]
Not used
R
Not used.
3
BAT_SHR
R/W
0
When this bit is high, a battery short circuit is detected.
2
IND_PEAK
R/W
0
When this bit is high, an inductor peak current-limit fault has occurred.
1
TSD_130
R/W
0
When this bit is high, the overtemperature early warning has occurred.
0
TSD_140
R/W
0
When this bit is high, the overtemperature condition is detected. The device shuts down due
to an overtemperature condition.
1
To reset the fault bits in the CHARGER_FAULT register, cycle the power on VBUSx, or read and then write the corresponding I2C bit high continuously.
Table 30. BATTERY_SHORT, Register Address 0x0B Bit Descriptions
Bit No.
Mnemonic
Access
Default
Description
[7:5]
TBAT_SHR[2:0]
R/W
100
Battery short timeout timer:
000 = 1 sec
001 = 2 sec
010 = 4 sec
011 = 10 sec
100 = 30 sec
101 = 60 sec
110 = 120 sec
111 = 180 sec



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