ADP5350ACPZ-1-R7 datasheet(60/63 Pages) AD

60 / 63 page

ADP5350

Data Sheet

Rev. B | Page 60 of 63

PCB LAYOUT GUIDELINES

Poor layout can affect ADP5350 performance, causing EMI and

electromagnetic compatibility (EMC) problems, ground bounce,

and voltage losses. Poor layout can also affect regulation and

stability. A good layout is implemented using the following

guidelines:



Place the decoupling capacitor, inductor, input capacitor,

and output capacitor close to the IC.



Use a ground plane with several vias connecting to the

component side ground to further reduce noise

interference on sensitive circuit nodes.



Use a dedicated trace to connect the BSNS pin to the

battery pack output node for accurate sensing of the

battery voltage.



Use Size 0603 or Size 0402 resistors and capacitors to

achieve the smallest possible footprint solution on boards

where space is limited.

Figure 59. Recommended Layout

nINT

THR

PGOOD

BSNS

ISOB

ISOS

AGND

PGND 1B SW 1A

SW 1B

VBUSA

VBUSB

PGND 4

SW4

FB4

VIN 4

VIN 123

CFL2

VOUT 3

SCL

VOUT 2

VOUT 1

BATOK

VOUT 4

CFL 1

ADP5350

SDA

PGND 1A

PGND

SCL

SDA

BATOK

nINT

1111

22222222

PGOOD

3333333

44444444

11888

1118888

888888888

C9 - 10µF

6.3V/XR5

0603

C10 - 10µF

25V/XR5

0603

C1 - 2.2µF

25V/XR5

0603

C2 - 2.2µF

6.3V/XR5

0603

C3 - 10µF

6.3V/XR5

0603

C4 - 10µF

6.3V/XR5

0603

L2 – 4µ7H

2016

L1 – 1µ5H

2016

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