ADA4099-1BUJZ-R5 datasheet(24/34 Pages) AD

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Data Sheet

ADA4099-1/ADA4099-2

APPLICATIONS INFORMATION

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Rev. A | 24 of 34

LARGE RESISTOR GAIN OPERATION

The ADA4099-1 and ADA4099-2 have approximately 12 pF of input

capacitance.

The parallel combination of the feedback resistor (RF) and gain set-

ting resistor (RG) on the inverting input can combine with this input

capacitance (CIN) to form a pole that can reduce bandwidth, cause

frequency response peaking, or produce oscillations (see Figure

61). To mitigate these consequences, place a feedback capacitor

with a value of CF > CIN(RG/RF) in parallel with RF for summing

node impedances >1 kΩ (RF||RG>1 kΩ). This capacitor placement

cancels the input pole and optimizes dynamic performance (see

Figure 60).

For applications where the noise gain is unity (RG→∞), and the

feedback resistor exceeds 1 kΩ, CF ≥ CIN. Optimize PCB layouts

to keep layout related summing node capacitance to an absolute

minimum.

Figure 60. Inverting Gain Schematic

Figure 61. Inverting Gain of 1, Small Signal Frequency Response, RF = RG =

10 kΩ

RECOMMENDED VALUES FOR VARIOUS

GAINS

Table 9 is a reference for determining various recommended gains

and associated noise performance. The total impedance seen at

the inverting input is kept to <1 kΩ for gains >1 to maintain ideal

small signal bandwidth.

Table 9. Gains and Associated Recommended Resistor Values (TA = 25°C)

Gain RG (kΩ)

RF (kΩ)

CF (pF)

Approximate −3 dB Frequency (MHz)

Total System Noise (nV/√Hz at 1 kHz), Referred to Input

Not applicable

6.8

7.2

8.2

2.7

4.02

1.5

7.4

−1

8.2

2.1

−1

4.8

14.4

−2

2.9

11.3

−5

4.99

1.4

9.2

−10

0.75

8.7

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