ADA4099-1BUJZ-R5 datasheet(26/34 Pages) AD

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Data Sheet

ADA4099-1/ADA4099-2

APPLICATIONS INFORMATION

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Rev. A | 26 of 34

in an inverting configuration, with the input common-mode biased at

midsupply.

POWER DISSIPATION AND THERMAL

SHUTDOWN

The ADA4099-1 and ADA4099-2 can drive heavy loads on power

supplies up to ±25 V. Therefore, ensure that TJ on the integrated

circuit does not exceed 175°C.

Junction temperatures exceeding 125°C promote accelerated ag-

ing. Reliability of the ADA4099-1 and ADA4099-2 may be impaired

if the junction temperature exceeds 175°C. If the junction tempera-

ture exceeds 175°C, the ADA4099-1 and ADA4099-2 have a final

safety measure in the form of a thermal shutdown that shuts off the

output stage and reduces the internal device currents. When this

thermal shutdown function triggers, the output remains disabled in

a high impedance state until the junction temperature drops 20°C.

Persistent heavy loads and elevated ambient temperatures can

cause the ADA4099-1 and ADA4099-2 to oscillate in and out of

thermal shutdown depending on the power dissipated on the die,

until the heavy load is removed (see Figure 64).

Figure 64. ADA4099-1 and ADA4099-2 Cycling In and Out of Thermal

Shutdown

It is not recommended to operate near the maximum junction

temperature.

Typically, TJ can be estimated from TA and the device power

dissipation (PD × θJA), as shown in the following equation:

TJ = TA + PD × θJA

The power dissipation in the IC varies as a function of supply

voltage, the output voltage, and load resistance. For a given supply

voltage, the worst case power dissipation (PD(MAX)) in the IC occurs

when the supply current is maximum, and the output voltage is at

half of either supply voltage.

PD(MAX) = VsIs(MAX)+ VSY2RL2

For a given supply voltage, use Figure 65 as a guide for estimating

the minimum load resistance that the ADA4099-1 and ADA4099-2

can drive for a given supply voltage and a given rise in junction

temperature (ΔTJ). For example, to limit ΔTJ to 50°C, the load

driven on the ±15 V supplies (+30 V total supply) must not be lower

than 1.2 kΩ. It is assumed that θJA is 192°C/W.

Figure 65. Minimum Load Resistance for Given ΔTJ and VSY

CIRCUIT LAYOUT CONSIDERATIONS

Careful and deliberate attention to detail when laying out the

ADA4099-1 and ADA4099-2 boards yields optimal performance.

Power supply bypassing, parasitic capacitance, and component

selection all contribute to the overall performance of the amplifiers.

POWER SUPPLY BYPASSING

On single supplies, solder the −VS supply pin directly to a low

impedance ground plane. Bypass the +VS pin to a low impedance

ground plane with a low effective series resistance (ESR) multilayer

ceramic capacitor (MLCC) of 0.1 µF, typically, as close to the ±VS

supply pins as possible. When driving heavy loads, add 10 µF of

supply capacitance. When using split supplies, these conditions are

applicable to the −VS supply pin.

The ADA4099-1 and ADA4099-2 have an internal current source

of ~0.6 μA on the SHDN (ADA4099-1) and SHDNx (ADA4099-2

10-lead LFCSP) pins to pull the pins down to −VS and place the

amplifiers in the default amplifying state. If the shutdown state is

not required, hard tie SHDN or SHDNx to the −VS pin. If SHDN or

SHDNx is left floating or driven by a source with significant source

impedance (>100 Ω), bypass the −VS supply pin with a small,

1 nF capacitor to prevent stray signals from coupling on SHDN or

SHDNx, which can inadvertently trigger shutdown.

GROUNDING

Use ground and power planes where possible to reduce the re-

sistance and inductance of the supply and ground returns. Place

bypass capacitors as close as possible to the ±VS supply pins, with

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