S80KS2563 datasheet(5/53 Pages) INFINEON

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Datasheet

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002-31339 Rev. *C

2021-09-27

256 Mb: HYPERRAM™ self-refresh dynamic RAM (DRAM) with Octal xSPI interface

1.8 V

General description

The 256 Mb HYPERRAM™ device is a high-speed CMOS, self-refresh DRAM, with xSPI (Octal) interface. The DRAM

array uses dynamic cells that require periodic refresh. Refresh control logic within the device manages the refresh

operations on the DRAM array when the memory is not being actively read or written by the xSPI interface master

(host). Since the host is not required to manage any refresh operations, the DRAM array appears to the host as

though the memory uses static cells that retain data without refresh. Hence, the memory is more accurately

described as pseudo static RAM (PSRAM).

Since the DRAM cells cannot be refreshed during a read or write transaction, there is a requirement that the host

limit read or write burst transfers lengths to allow internal logic refresh operations when they are needed. The

host must confine the duration of transactions and allow additional initial access latency, at the beginning of a

new transaction, if the memory indicates a refresh operation is needed.

1.1

xSPI (Octal) interface

xSPI (Octal) is a SPI-compatible low signal count, DDR interface supporting eight I/Os. The DDR protocol in xSPI

(Octal) transfers two data bytes per clock cycle on the DQ input/output signals. A read or write transaction on

xSPI (Octal) consists of a series of 16-bit wide, one clock cycle data transfers at the internal RAM array with two

corresponding 8-bit wide, one-half-clock-cycle data transfers on the DQ signals. All inputs and outputs are

LV-CMOS compatible. Device are available as 1.8 V VCC/VCCQ (nominal) for array (VCC) and I/O buffer (VCCQ)

supplies, through different ordering part number (OPN).

Each transaction on xSPI (Octal) must include a command whereas address and data are optional. The transac-

tions are structures as follows:

• Each transaction begins with CS# going LOW and ends with CS# returning HIGH.

• The serial clock (CK) marks the transfer of each bit or group of bits between the host and memory. All transfers

occur on every CK edge (DDR mode).

• Each transaction has a 16-bit command which selects the type of device operation to perform. The 16-bit

command is based on two 8-bit opcodes. The same 8-bit opcode is sent on both edges of the clock.

• A command may be stand-alone or may be followed by address bits to select a memory location in the device

to access data.

• Read transactions require a latency period after the address bits and can be zero to several CK cycles. CK must

continue to toggle during any read transaction latency period. During the command and address parts of a

transaction, the memory can indicate whether an additional latency period is needed for a required refresh time

(tRFH) which is added to the initial latency period; by driving the RWDS signal to the HIGH state.

• Write transactions to registers do not require a latency period.

• Write transactions to the memory array require a latency period after the address bits and can be zero to several

CK cycles. CK must continue to toggle during any write transaction latency period. During the command and

address parts of a transaction, the memory can indicate whether an additional latency period is needed for a

required refresh time (tRFH) which is added to the initial latency period by driving the RWDS signal to the HIGH

state.

• In all transactions, command and address bits are shifted in the device with the most significant bits (MSb) first.

The individual data bits within a data byte are shifted in and out of the device MSb first as well. All data bytes

are transferred with the lowest address byte sent out first.

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