S80KS2563 datasheet(9/53 Pages) INFINEON

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Datasheet

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002-31339 Rev. *C

2021-09-27

256 Mb: HYPERRAM™ self-refresh dynamic RAM (DRAM) with Octal xSPI interface

1.8 V

Signal description

3.1

Input/output summary

The xSPI (Octal) HYPERRAM™ signals are shown in Table 1. Active low signal names have a hash symbol (#) suffix.

Table 1

I/O summary

Symbol

Type

Description

CS#

Input

Chip select. Bus transactions are initiated with a HIGH to LOW

transition. Bus transactions are terminated with a Low to High

transition. The master device has a separate CS# for each slave.

CK, CK#[9]

Input

Differential clock. Command, address, and data information is output

with respect to the crossing of the CK and CK# signals. Use of

differential clock is optional.

Single ended clock. CK# is not used, only a single ended CK is used.

The clock is not required to be free-running.

DQ[7:0]

Input/output

Data input/output. Command, address, and data information is

transferred on these signals during read and write transactions.

RWDS

Input/output

Read-write data strobe. During the command/address portion of all

bus transactions RWDS is a slave output and indicates whether

additional initial latency is required. Slave output during read data

transfer, data is edge-aligned with RWDS. Slave input during data

transfer in write transactions to function as a data mask.

(HIGH = additional latency, LOW = no additional latency).

RESET#

Input, internal pull-up

Hardware RESET. When LOW, the slave device will self initialize and

return to the standby state. RWDS and DQ[7:0] are placed into the

HIGH-Z state when RESET# is LOW. The slave RESET# input includes a

weak pull-up, if RESET# is left unconnected it will be pulled up to the

HIGH state.

VCC

Power supply

Array power.

VCCQ

Power supply

Input/output power.

VSS

Power supply

Array ground.

VSSQ

Power supply

Input/output ground.

RFU

No connect

Reserved for future use. May or may not be connected internally, the

signal/ball location should be left unconnected and unused by PCB

routing channel for future compatibility. The signal/ball may be used

by a signal in the future.

Note

9. CK# is used in differential clock mode, but optional connection. Tie the CK# input pin to either VCCQ or VSSQ

if not connected to the host controller, but do not leave it floating.

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