STA335BWSQS datasheet(20/70 Pages) STMICROELECTRONICS

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I2C bus specification

STA335BWSQS

20/70

I2C bus specification

The STA335BWSQS supports the I2C protocol via the input ports SCL and SDA_IN (master

to slave) and the output port SDA_OUT (slave to master). This protocol defines any device

that sends data on to the bus as a transmitter and any device that reads the data as a

receiver. The device that controls the data transfer is known as the master and the other as

the slave. The master always starts the transfer and provides the serial clock for

synchronization. STA335BWSQS is always a slave device in all of its communications. It

supports up to 400 kb/s (fast-mode bit rate). STA335BWSQS I2C is a slave only interface.

5.1

Communication protocol

5.1.1

Data transition or change

Data changes on the SDA line must only occur when the SCL clock is low. SDA transition

while the clock is high is used to identify a START or STOP condition.

5.1.2

Start condition

START is identified by a high to low transition of the data bus SDA signal while the clock

signal SCL is stable in the high state. A START condition must precede any command for

data transfer.

5.1.3

Stop condition

STOP is identified by low to high transition of the data bus SDA signal while the clock signal

SCL is stable in the high state. A STOP condition terminates communication between

STA335BWSQS and the bus master.

5.1.4

Data input

During the data input the STA335BWSQS samples the SDA signal on the rising edge of

clock SCL. For correct device operation the SDA signal must be stable during the rising

edge of the clock and the data can change only when the SCL line is low.

5.2

Device addressing

To start communication between the master and the STA335BWSQS, the master must

initiate with a start condition. Following this, the master sends onto the SDA line 8-bits (MSB

first) corresponding to the device select address and read or write mode.

The seven most significant bits are the device address identifiers, corresponding to the I2C

bus definition. In the STA335BWSQS the I2C interface has two device addresses depending

on the SA port configuration, 0x38 when SA = 0, and 0x3A when SA = 1.

The eighth bit (LSB) identifies read or write operation RW, this bit is set to 1 in read mode

and 0 for write mode. After a START condition the STA335BWSQS identifies on the bus the

device address and if a match is found, it acknowledges the identification on SDA bus during

the 9th bit time. The byte following the device identification byte is the internal space

address.

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