| Datenblatt-Suchmaschine für elektronische Bauteile |
|
STA335BWSQS Datenblatt(PDF) 30 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
STA335BWSQS Datenblatt(HTML) 30 Page - STMicroelectronics |
|
30 / 70 page ![]() Register description STA335BWSQS 30/70 6.2.5 Channel input mapping Each channel received via I2S can be mapped to any internal processing channel via the Channel Input Mapping registers. This allows for flexibility in processing. The default settings of these registers map each I2S input channel to its corresponding processing channel. 6.3 Configuration register C (addr 0x02) 6.3.1 DDX® power output mode The DDX power output mode selects how the DDX output timing is configured. Different power devices use different output modes. Table 21. CnIM Bit RW RST Name Description 6RW 0 C1IM 0: Processing channel 1 receives Left I2S Input 1: Processing channel 1 receives Right I2S Input 7RW 1 C2IM 0: Processing channel 2 receives Left I2S Input 1: Processing channel 2 receives Right I2S Input D7 D6 D5 D4 D3 D2 D1 D0 OCRB Reserved CSZ3 CSZ2 CSZ1 CSZ0 OM1 OM0 1 0 1 011 1 Table 22. OM Bit RW RST Name Description 0RW 1 OM0 Selects configuration of DDX output. 1RW 1 OM1 Table 23. Output modes OM[1,0] Output stage mode 00 Drop compensation 01 Discrete output stage - tapered compensation 10 Full power mode 11 Variable drop compensation (CSZx bits) |
|
Link URL |
| War ALLDATASHEET hilfreich? [ DONATE ] |
Über Alldatasheet | Werbung | Kontakt | Privatsphäre und Datenschutz | Link zum Datenblatt | Linktausch | Hersteller All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |