STA335BWSQS datasheet(41/70 Pages) STMICROELECTRONICS

41 / 70 page

STA335BWSQS

41/70

6.6.3

Binary output mode clock loss detection

Detects loss of input MCLK in binary mode and will output 50% duty cycle.

6.6.4

LRCK double trigger protection

Actively prevents double trigger of LRCLK.

6.6.5

Auto EAPD on clock loss

When active, issues a power device power down signal (EAPD) on clock loss detection.

6.6.6

IC power down

The PWDN register is used to place the IC in a low-power state. When PWDN is written

as 0, the output begins a soft-mute. After the mute condition is reached, EAPD is asserted

to power down the power-stage, then the master clock to all internal hardware expect the

I2C block is gated. This places the IC in a very low power consumption state.

6.6.7

External amplifier power down

The EAPD register directly disables/enables the internal power circuitry.

When EAPD = 0, the internal power section is placed on a low-power state (disabled). This

Table 46.

BCLE

Bit

RST

Name

Description

BCLE

Binary output mode clock loss detection enable

Table 47.

LDTE

Bit

RST

Name

Description

LDTE

LRCLK double trigger protection enable

Table 48.

ECLE

Bit

RST

Name

Description

ECLE

Auto EAPD on clock loss

Table 49.

PWDN

Bit

RST

Name

Description

7RW

PWDN

0: IC power down low-power condition

1: IC normal operation

Table 50.

EAPD

Bit

RST

Name

Description

EAPD

0: External power stage power down active

1: Normal operation

STA335BWSQS Datenblatt(PDF) 41 Page - STMicroelectronics

STA335BWSQS Datenblatt(HTML) 41 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datenblatt Download

Link URL