48LM01 datasheet(18/40 Pages) MICROCHIP

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DS20006008C-page 18

48L512/48LM01

8.0

WRITE COMMANDS

In order to write to the SRAM in the 48L512/48LM01,

the device must be write-enabled via the Write Enable

(WREN) instruction. If the device is not Write Enabled

(WREN), the device will ignore the SRAM WRITE

instruction and will return to the Standby state when CS

is brought high. Each unique write to the SRAM array

is not immediately transferred to EEPROM so there is

no delay after one write to begin another SRAM

read/write operation. Contents of the SRAM are only

automatically transferred to EEPROM on any power

disruption. The user may also force a transfer from

SRAM to EEPROM using the Software Store command

or at power-down with AutoStore. (see Section 11.3

"Software Store Command").

8.1

Write Instruction Sequences

8.1.1

SRAM BYTE WRITE

Once a WREN command has been completed, an

SRAM byte write sequence can be performed as

shown in Figure 8-1. After the CS line is pulled low to

select the device, the opcode is transmitted via the SI

line, followed by the rest of up to 16- or 24-bit address

and the data (D7-D0) to be programmed, depending on

the device.

The 48L512/48LM01 is automatically returned to the

Write Disable state (STATUS register bit WEL = 0) at

the completion of an SRAM write operation.

FIGURE 8-1:

SRAM BYTE WRITE WAVEFORM

Note:

If the CS pin is deselected at somewhere

other than the end of an 8-bit byte

boundary, the incomplete SRAM byte

write will be aborted. Data written is using

the WRITE instruction to the SRAM array.

SCK

02 3 4

5 6 7

WRITE Opcode

D7 D6 D5 D4 D3 D2 D1 D0

Data In

MSb

High-Impedance

Address (2 or 3 bytes)

A A AAA

MSb

AAA

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