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48LM01 Datenblatt(PDF) 17 Page - Microchip Technology |
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48LM01 Datenblatt(HTML) 17 Page - Microchip Technology |
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17 / 40 page ![]() 2018-2019 Microchip Technology Inc. DS20006008C-page 17 48L512/48LM01 7.0 READ OPERATIONS 7.1 Reading from the SRAM (READ) Reading the SRAM contents can be done whenever the device is not in an internal store or recall cycle, as indicated by the Ready/Busy bit of the STATUS register. To read the SRAM, first the CS line is pulled low to select the device and the Read opcode 03h is transmitted via the SI line followed by the 16- or 24-bit address to be read. Upon completion of the address bytes, any data on the SI line will be ignored. The data (D7–D0) at the specified address is then shifted out onto the SO line. Any number of bytes can be clocked out, and if the address reaches the end of the array, it can continue at the beginning of the array. Read operations are not limited by page boundaries. The read sequence can be terminated at any point of the operation. The CS line should be driven high after the data is clocked out. FIGURE 7-1: READ SRAM (READ) WAVEFORM CS SCK 1 02 3 4 5 6 00 0 0 0 01 1 READ Opcode Address Bits (24/16) AA A A A SI D7 Data Byte SO MSb MSb MSb High-Impedance AAA 7 D6 D5 D4 D3 D2 D1 D0 |
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