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48LM01 Datenblatt(PDF) 14 Page - Microchip Technology

Teilenummer 48LM01
Bauteilbeschribung  512-Kbit/1-Mbit SPI Serial EERAM
PDF  40 Pages
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Hersteller  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
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48LM01 Datenblatt(HTML) 14 Page - Microchip Technology

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 2018-2019 Microchip Technology Inc.
DS20006008C-page 14
48L512/48LM01
6.0
STATUS REGISTER
The 48L512/48LM01 includes a 1-byte STATUS
register which is a combination of four nonvolatile bits
and four volatile bits. The STATUS register bits control
or indicate various features of the device as shown in
Register 6-1. These bits can be read or modified by
specific instructions that are detailed in the subsequent
sections.
6.1
Block Write-Protect Bits
The 48L512/48LM01 contains four levels of SRAM
write protection using the block protection function. The
nonvolatile Block Write-Protect bits (BP1, BP0) are
located in bits three and two of the STATUS register
byte and define the region of the SRAM that are to be
treated as read-only.
The address ranges that are protected for each SRAM
Block Write Protection level and the corresponding
STATUS register control bits are shown in Table 6-2.
REGISTER 6-1:
STATUS REGISTER
R/W
R/W
R/W
R-0
R/W
R/W
R-0
R-0
Reserved
ASE
Reserved
SWM
BP1
BP0
WEL
RDY/BSY
bit 7
bit 0
Legend:
R = Readable bit
W = Writable bit
U = Unimplemented bit, read as ‘0’
-n = Value at POR
‘1’ = Bit is set
‘0’ = Bit is cleared
x = Bit is unknown
bit 7
Reserved: Must be set to ‘0’
bit 6
ASE: AutoStore Enable bit
1
= AutoStore is disabled.
0
= AutoStore is enabled (factory default).
bit 5
Reserved: Must be set to ‘0’
bit 4
SWM: Secure Write Monitoring bit – Read-Only
1
= The last secure write operation has failed.
0
= No error reported in Secure Write.
bit 3-2
BP[1:0]: Block Protection bits (see Table 6-2)
00
= (Level 0) No SRAM array write protection (factory default)
01
= (Level 1) Upper quarter SRAM memory array protection
10
= (Level 2) Upper half SRAM memory array protection
11
= (Level 3) Entire SRAM memory array protection
bit 1
WEL: Write Enable Latch bit – Read-Only
1
= WREN has been executed and device is enabled for writing.
0
= Device is not write-enabled.
bit 0
RDY/BSY: Ready/Busy Status bit – Read-Only
1
= Device is busy with an internal store or recall operation.
0
= Device is ready for standard SRAM Read/Write commands.



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