LTC2445 datasheet(15/28 Pages) LINER

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LTC2444/LTC2445/

LTC2448/LTC2449

sn2444589 2444589fs

Speed Multiplier Mode

In addition to selecting the speed/resolution, a speed

multiplier mode is used to double the output rate while

maintaining the selected resolution. The last bit of the 5-bit

speed/resolution control word (TWOX, see Table 5) deter-

mines if the output rate is 1X (no speed increase) or 2X

(double the selected speed).

While operating in the 1X mode, the device combines two

internal conversions for each conversion result in order to

remove the ADC offset. Every conversion cycle, the offset

and offset drift are transparently calibrated greatly simpli-

fying the user interface. The resulting conversion result

has no latency. The first conversion following a newly

selected speed/resolution and input channel is valid. This

is identical to the operation of the LTC2440, LTC2414 and

LTC2418.

While operating in the 2X mode, the device performs a

running average of the last two conversion results. This

automatically removes the offset and drift of the device

while increasing the output rate by 2X. The resolution

(noise) remains the same. If a new channel is selected, the

conversion result is valid for all conversions after the first

conversion (one cycle latency). If a new speed/resolution

is selected, the first conversion result is valid but the

resolution (noise) is a function of the running average. All

subsequent conversion results are valid. If the mode is

changed from either 1X to 2X or 2X to 1X without changing

the resolution or channel, the first conversion result is

valid.

If an external buffer/amplifier circuit is used for the

LTC2445/LTC2449, the 2X mode can be used to increase

the settling time of the amplifier between readings. While

operating in the 2X mode, the multiplexer output (input to

the external buffer/amplifier) is switched at the end of each

conversion cycle. Prior to concluding the data out/in cycle,

the analog multiplexer output is switched. This occurs at

the end of the conversion cycle (just prior to the data

output cycle) for auto calibration. The time required to

read the conversion enables more settling time for the

external buffer/amplifier. The offset/offset drift of the

external amplifier is automatically removed by the

converter’s auto calibration sequence for both the 1X and

2X speed modes.

While operating in the 1X mode, if a new input channel is

selected the multiplexer is switched on the falling edge of

the 14th SCK (once the complete data input word is

programmed). The remaining data output sequence time

can be used to allow the external buffer/amplifier to settle.

BUSY

The BUSY output (Pin 2) is used to monitor the state of

conversion, data output and sleep cycle. While the part is

converting, the BUSY pin is HIGH. Once the conversion is

complete, BUSY goes LOW indicating the conversion is

complete and data out is ready. The part now enters the

LOW power sleep state. BUSY remains LOW while data is

shifted out of the device and SDI is shifted into the device.

It goes HIGH at the conclusion of the data input/output

cycle indicating a new conversion has begun. This rising

edge may be used to flag the completion of the data read

cycle.

SERIAL INTERFACE TIMING MODES

The LTC2444/LTC2445/LTC2448/LTC2449’s 3- or 4-wire

interface is SPI and MICROWIRE compatible. This inter-

face offers several flexible modes of operation. These in-

clude internal/external serial clock, 3- or 4-wire I/O, single

cycle conversion and autostart. The following sections

describe each of these serial interface timing modes in

detail. In all these cases, the converter can use the internal

oscillator (FO = LOW) or an external oscillator connected

to the FO pin. Refer to Table 6 for a summary.

Table 6. LTC2444/LTC2445/LTC2448/LTC2449 Interface Timing Modes

Conversion

Data

Connection

SCK

Cycle

Output

and

Configuration

Source

Control

Waveforms

External SCK, Single Cycle Conversion

External

CS and SCK

Figures 4, 5

External SCK, 2-Wire I/O

External

SCK

Figure 6

Internal SCK, Single Cycle Conversion

Internal

CS ↓

Figures 7, 8

Internal SCK, 2-Wire I/O, Continuous Conversion

Internal

Continuous

Internal

Figure 9

APPLICATIO S I FOR ATIO

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