AD6654BBCZ datasheet(56/88 Pages) AD

56 / 88 page

AD6654

Rev. 0 | Page 56 of 88

PARALLEL PORT PIN FUNCTIONS

Table 25 describes the functions of the pins used by the parallel ports.

Table 25. Parallel Port Pin Functions

Pin Name

I/O

Function

PCLK

I/O

Parallel Clock. PCLK can operate as a master or as a slave. This setting is dependent on the 1-bit PCLK master

mode bit in the Parallel Port Control 2 register. As an output (master mode), the maximum frequency is

CLK/N, where CLK is the AD6654 clock and N is an integer divisor of 1, 2, 4, or 8. As an input (slave mode), it

can be asynchronous or synchronous relative to the AD6654 CLK. This pin powers up as an input to avoid

possible contentions. Parallel port output pins change on the rising edge of PCLK.

PAREQ, PBREQ,

PCREQ

Active High Output. Synchronous to PCLK. A logic high on this pin indicates that data is available to be

shifted out of the port. When an acknowledge signal is received, data starts shifting out and this pin remains

high until all pending data has been shifted out.

PAACK, PBACK,

PCACK

Active High Asynchronous Input. Applying a logic low on this pin inhibits parallel port data shifting. Applying

a logic high to this pin when REQ is high causes the parallel port to shift out data according to the

programmed data mode. ACK is sampled on the rising edge of PCLK. Assuming that REQ is asserted, the

latency from the assertion of ACK to data appearing at the parallel port output is no more than 1.5 PCLK

cycles. ACK can be continuously held high; in this case, when data becomes available, shifting begins 1 PCLK

cycle after the assertion of REQ (see Figure 57, Figure 58, Figure 59, and Figure 60).

PAIQ, PBIQ, PCIQ

Parallel Output Gain Data Indicators High whenever I data is present on the parallel port data bus; otherwise

low. In parallel I/Q mode, both I data and Q data are available at the same time and, therefore, the PxIQ signal

is pulled high.

PAGAIN, PBGAIN,

PCGAIN

Parallel Output Gain Word Indicators. High whenever the AGC gain word is present on the parallel port data

bus; otherwise low.

PACH[2:0], PBCH[2:0],

PCCH[2:0]

Channel Indicator Output Ports. These pins identify data in both of the parallel port modes. The 3-bit value

identifies the source of the data (AGC number) on the parallel port when it is being shifted out.

PADATA[15:0],

PBDATA[15:0],

PCDATA[15:0]

Parallel Output Port Data Bus. Output format is twos complement. In parallel I/Q mode, 8-bit data is present;

in interleaved I/Q mode, 16-bit data is available.

AD6654BBCZ Datenblatt(PDF) 56 Page - Analog Devices

AD6654BBCZ Datenblatt(HTML) 56 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88

Datenblatt Download

Link URL