AD6654BBCZ datasheet(83/88 Pages) AD

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AD6654

Rev. 0 | Page 83 of 88

When this bit is cleared, AGC5 data does not appear on Output

Port C.

<20>: Port C, AGC4 Enable Bit. Similar to Bit 21 for AGC4.

<19>: Port C, AGC3 Enable Bit. Similar to Bit 21 for AGC3.

<18>: Port C, AGC2 Enable Bit. Similar to Bit 21 for AGC2.

<17>: Port C, AGC1 Enable Bit. Similar to Bit 21 for AGC1.

<16>: Port C, AGC0 Enable Bit. Similar to Bit 21 for AGC0.

<15>: Port B Append RSSI Bit. When this bit is set, an RSSI

word is appended to every I/Q output sample, regardless of

whether the RSSI word is updated in the AGC. When this bit is

cleared, an RSSI word is appended to an I/Q output sample only

when the RSSI word is updated. The RSSI word is not output for

subsequent I/Q samples until the next time the RSSI is updated

in the AGC.

<14>: Port B, Data Format Bit. When this bit is set, the port is

configured for 8-bit parallel I/Q mode. When this bit is cleared,

the port is configured for 16-bit interleaved I/Q mode. See the

Parallel Port Output section.

<13>: Port B, AGC5 Enable Bit. When this bit is set, AGC5 data

(I/Q data) is output on Parallel Output Port A (data bus). When

this bit is cleared, AGC5 data does not appear on Output Port

<12>: Port B, AGC4 Enable Bit. Similar to Bit 13 for AGC4.

<11>: Port B, AGC3 Enable Bit. Similar to Bit 13 for AGC3.

<10>: Port B, AGC2 Enable Bit. Similar to Bit 13 for AGC2.

<9>: Port B, AGC1 Enable Bit. Similar to Bit 13 for AGC1.

<8>: Port B, AGC0 Enable Bit. Similar to Bit 13 for AGC0.

<7>: Port A Appended RSSI Bit. When this bit is set, an RSSI

word is append to every I/Q output sample, regardless of

whether the RSSI word is updated in the AGC. When this bit is

cleared, an RSSI word is appended to an I/Q output sample only

when the RSSI word is updated. The RSSI word is not output for

subsequent I/Q samples until the next time RSSI is updated

again in the AGC.

<6>: Port A, Data Format Bit. When this bit is set, the port is

configured for 8-bit parallel I/Q mode. When this bit is cleared,

the port is configured for 16-bit interleaved I/Q mode. See the

Parallel Port Output section.

<5>: Port A, AGC5 Enable Bit. When this bit is set, AGC5 data

(I/Q data) is output on parallel output Port A (data bus). When

this bit is cleared, AGC5 data does not appear on output Port C.

<4>: Port A, AGC4 Enable Bit. Similar to Bit 5 for AGC4.

<3>: Port A, AGC3 Enable Bit. Similar to Bit 5 for AGC3.

<2>: Port A, AGC2 Enable Bit. Similar to Bit 5 for AGC2.

<1>: Port A, AGC1 Enable Bit. Similar to Bit 5 for AGC1.

<0>: Port A, AGC0 Enable Bit. Similar to Bit 5 for AGC0.

Output Port Control <9:0>

<9:8>: PCLK Divisor Bits. When a parallel port is in master

mode, the PCLK is derived from the PLL_CLK. These bits

define the value of the divisor used to divide the PLL_CLK to

obtain the PCLK. These bits are don’t care in slave mode.

Table 42. PCLK Divisor Bits

PCLK Divisor <7:6>

Divisor Value

<7>: PCLK Master Mode Bit. When the PCLK master mode bit

is set, the PCLK pin is configured as an output and the PCLK is

driven by the PLL_CLK. Data is transferred out of the AD6654

synchronous to this output clock. When this bit is cleared, the

PCLK pin is configured as an input. The user is required to

provide a PCLK, and data is transferred out of the AD6654

synchronous to this input clock. On power-up, this bit is cleared

to avoid contention on the PCLK pin.

<6:4>: Reserved. These bits must be written with Logic 0.

<3:0>: Stream Control Bits. These bits are described in Table 43.

Table 43. Stream Control Bits

Stream

Control

Bits

Output Streams (str0, str1, str2,

str3, str4, str5)

Number of

Streams

0000

Ch 0 and Ch 1 combined; Ch 2, Ch 3,

Ch 4, Ch 5 independent

0001

Ch 0, Ch 1, Ch 2 combined; Ch 3, Ch 4,

Ch 5 independent

0010

Ch 0, Ch 1, Ch 2, Ch 3 combined; Ch 4,

Ch 5 independent

0011

Ch 0, Ch 1, Ch 2, Ch 3, Ch 4 combined;

Ch 5 independent

0100

Ch 0, Ch 1, Ch 2, Ch 3, Ch 4, Ch 5

combined

0101

Ch 0, Ch 1, Ch 2 combined; Ch 3, Ch 4,

Ch 5 combined

0110

Ch 0, Ch 1 combined; Ch 2, Ch 3

combined; Ch 4, Ch 5 combined

0111

Ch 0, Ch 1 combined; Ch 2, Ch 3

combined; Ch 4, Ch 5 independent

1000

Ch 0, Ch 1 , Ch 2 combined; Ch 3, Ch 4

combined; Ch 5 independent

1001

Ch 0, Ch 1, Ch 2, Ch 3 combined; Ch 4,

Ch 5 combined.

Default

Independent channels

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