AD6654BBCZ datasheet(79/88 Pages) AD

79 / 88 page

AD6654

Rev. 0 | Page 79 of 88

CIC Decimation <4:0>

This 5-bit word specifies the CIC filter decimation value

minus 1. A value of 0x00 is a decimation of 1 (bypass), and

0x1F is a decimation of 32. Writing a value of 0 in this register

bypasses CIC filtering, but does not bypass the CIC scaling

operation.

CIC Scale Factor <4:0>

This 5-bit word specifies the CIC filter scale factor used to

compensate for the gain provided by the CIC filter. The

recommended value is given by the following equation:

))

(

log

(

−

CIC

ceil

Scale

CIC

where:

MCIC

is the decimation rate of the CIC (one more than the value

in the CIC decimation register).

ceil

operation gives the closest integer greater than or equal to

the argument.

The valid range for this register is decimal 0 to 20.

FIR-HB Control <3:0>

<3>: FIR1 Enable Bit. When this bit is set, the FIR1 fixed

coefficient filter is enabled. When cleared, FIR1 is bypassed.

<2>: HB1 Enable Bit. When this bit is set, the HB1 half-band

filter is enabled. When cleared, HB1 is bypassed.

<1>: FIR2 Enable Bit. When this bit is set, the FIR2 fixed

coefficient filter is enabled. When cleared, FIR2 is bypassed.

<0>: HB2 Enable Bit. When this bit is set, the HB2 half-band

filter is enabled. When cleared, HB2 is bypassed.

MRCF Control Register <12:0>

<12:10>: MRCF Data Select Bits. These bits are used to select

the input source for the MRCF filter. Each MRCF filter can be

driven by output from the HB2 filter of any channel independ-

ently. Table 35 shows the selections available.

Table 35. MRCF Data Select Bits

MRCF Data Select<2:0>

MRCF Input Source

000

MRCF input taken from Channel 0

001

MRCF input taken from Channel 1

010

MRCF input taken from Channel 2

011

MRCF input taken from Channel 3

1x0

MRCF input taken from Channel 4

1x1

MRCF input taken from Channel 5

<9>: Interpolating Half-Band Enable Bit. When this bit is set,

the interpolating half-band filter, driven by the output of the

CRCF block, is enabled. When cleared, the interpolating half-

band filter is bypassed, and its output is the same as its input.

The interpolating half-band filter doubles the data rate.

<8>: This bit is open.

<7>: Half-Rate Bit. When this bit is set, the MRCF filter

operates using half the PLL clock rate. This is used for power

savings when there is sufficient time to complete MRCF

filtering using only half the PLL clock rate. When this bit is

cleared, the MRCF filter operates at the full PLL clock rate. See

the Mono-Rate RAM Coefficient Filter (MRCF) section.

<6:4>: MRCF Number of Taps Bits. This 3-bit word should be

written with one less than the number of taps that are calculated

by the MRCF filter. The filter length is given by the decimal

value of this register plus 1. A value of 0 represents a 1-tap filter

and maximum value of 7 represents an 8-tap filter.

<3:2>: MRCF Scale Factor Bits. The output of the MRCF filter is

scaled according to the value of these bits. Table 36 describes

the attenuation corresponding to each setting.

Table 36. MRCF Scale Factor

MRCF Scale<1:0>

Scale Factor

18.06 dB attenuation (left-shift 3 bits)

12.04 dB attenuation (left-shift 2 bits)

6.02 dB attenuation (left-shift 1 bit)

No scaling (0 dB)

<1>: This bit is open.

<0>: MRCF Bypass Bit. When this bit is set, the MRCF filter is

bypassed and, therefore, the output of the MRCF is the same as

its input. When this bit is cleared, the MRCF has normal

operation as programmed by its control register.

MRCF COEFFICIENT MEMORY

The MRCF coefficient memory consists of eight coefficients,

each six bits wide. The memory extends from Address 0x80 to

Address 0x87. The coefficients should be written in twos

complement format.

DRCF Control Register <11:0>

<11>: DRCF Bypass Bit. When this bit is set, the DRCF filter is

bypassed and, therefore, its output is the same as its input.

When this bit is cleared, the DRCF has normal operation as

programmed by the rest of this control register.

<10>: Symmetry Bit. When this bit is set, it indicates that the

DRCF is implementing a symmetrical filter and only half the

impulse response needs to be written into the DRCF coefficient

RAM. When this bit is cleared, the filter is asymmetrical and

complete impulse response of the filter should be written to the

coefficient RAM. When this filter is symmetrical, it can imple-

ment up to 128 filter taps.

<9:8>: DRCF Multiply Accumulate Scale Bits. The output of the

DRCF filter is scaled according to the value of these bits.

Table 37 lists the attenuation corresponding to each setting.

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