AD6654BBCZ datasheet(30/88 Pages) AD

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AD6654

Rev. 0 | Page 30 of 88

input clock cycle, as long as the input signal remains below the

lower threshold register value. If the counter reaches 1, the gain

control output is incremented by 1. If the signal goes above the

lower threshold register value, the gain adjustment is not made,

and the normal comparison to lower and upper threshold

registers is initiated once again. Therefore, the dwell timer

provides temporal hysteresis and prevents the gain from

continuously switching.

In a typical application, if the ADC signal goes below the lower

threshold for a time greater than the dwell time, then the gain

control output is incremented by 1. Gain control bits control the

gain ranging block, which appears before the ADC in the signal

chain. With each increment of the gain control output, gain in

the gain-ranging block is increased by 6.02 dB. This increases

the dynamic range of the input signal into the ADC by 6.02 dB.

This gain is compensated for in the AD6654 by relinearizing, as

explained in the Relinearization section. Therefore, the AD6654

can increase the dynamic range of the ADC by 42 dB, provided

that the gain-ranging block can support it.

Relinearization

The gain in the gain-ranging block (external) is compensated

for by relinearizing, using the exponent bits EXP[2:0] of the

input port. For this purpose, the gain control bits are connected

to the EXP[2:0] bits, providing an attenuation of 6.02 dB for

every increase in the gain control output. After the gain in the

external gain-ranging block and the attenuation in the AD6654

(using EXP bits), the signal gain is essentially unchanged. The

only change is the increase in the dynamic range of the ADC.

External gain-ranging blocks have a delay associated with

changing the gain of the signal. Typically, these delays can be

up to 14 clock cycles. The gain change in the AD6654 (via

EXP[2:0]) must be synchronized with the gain change in the

gain-ranging block (external). This is allowed in the AD6654 by

providing a flexible delay, programmable 6-bit word in the gain

control register. The value in this 6-bit word gives the delay in

input clock cycles. A programmable pipeline delay given by the

6-bit value (maximum delay of 63 clock cycles) is placed

between the gain control output and the EXP[2:0] input.

Therefore, the external gain-ranging block’s settling delays

are compensated for in the AD6654.

Note that any gain changes that are initiated during the relinear-

ization period are ignored. For example, if the AD6654 detects

that a gain adjustment is required during the relinearization

period of a previous gain adjustment, then the new adjustment

is ignored.

Setting Up the Gain Control Block

To set up the gain control block for the input port, the individ-

ual upper threshold registers and lower threshold registers

should be written with appropriate values. The 10-bit values

written into upper and lower threshold registers are compared

to the 10 MSBs of the absolute magnitude calculated using the

input port data. The 20-bit dwell-time register should have the

appropriate number of clock cycles to provide temporal

hysteresis.

A 6-bit relinearization pipeline delay word is set to synchronize

with the settling delay in the external gain-ranging circuitry.

Finally, the gain control enable bit is written with Logic 1 to

activate the gain control block. On enabling, the gain control

output bits are made 000 (output on EXP[2:0] pins), which

represent the minimum gain for the external gain-ranging

circuitry and corresponding minimum attenuation during

relinearization. The normal functioning takes over, as explained

previously in this section.

DWELL

TIMER

COMPARE

< B

DEC

INC

EXP GEN

FROM

MEMORY

MAP

EXP [2:0]

LOWER

THRESHOLD

COMPARE

> B

FROM

MEMORY

MAP

UPPER

THRESHOLD

FROM INPUT

PORTS

INCREASE

EXTERNAL GAIN

DECREASE

EXTERNAL GAIN

Figure 43. Gain Control Block Diagram

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