A0

A1

RESET

INT0

SD0

SC0

GND

VCC

SDA

SCL

INT

SC1

SD1

INT1

V

DPU0

VIA to Power Plane

Partial Power Plane

V

DPU1

V

DPUM

VIA to GND Plane (Inner Layer)

Polygonal

Copper Pour

V

CC

GND

By-pass/De-coupling

capacitors

GND

To I2C Master

LEGEND

22

TCA9543A

SCPS206B – MARCH 2014 – REVISED NOVEMBER 2019

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Copyright © 2014–2019, Texas Instruments Incorporated

11 Layout

11.1 Layout Guidelines

For PCB layout of the TCA9543A, common PCB layout practices should be followed but additional concerns

related to high-speed data transfer such as matched impedances and differential pairs are not a concern for I2C

signal speeds. It is common to have a dedicated ground plane on an inner layer of the board and terminals that

are connected to ground should have a low-impedance path to the ground plane in the form of wide polygon

pours and multiple vias. By-pass and de-coupling capacitors are commonly used to control the voltage on the

VCC terminal, using a larger capacitor to provide additional power in the event of a short power supply glitch and

a smaller capacitor to filter out high-frequency ripple.

In an application where voltage translation is not required, all VDPUX voltages and VCC could be at the same

potential and a single copper plane can connect all of the pull-up resistors to the appropriate reference voltage.

In an application where voltage translation is required, VDPUM, VDPU0, and VDPU1, may all be on the same layer of

the board with split planes to isolate different voltage potentials.

To reduce the total I2C bus capacitance added by PCB parasitics, data lines (SCn, SDn and INTn) should be a

short as possible and the widths of the traces should also be minimized (e.g. 5-10 mils depending on copper

weight).

11.2 Layout Example

Figure 23. Layout Example