STA380WS datasheet(28/48 Pages) STMICROELECTRONICS

28 / 48 page

STA380WS

28/48

DocID024426 Rev 1

Channel input mapping

Each channel received via I2S can be mapped to any internal processing channel via the

channel input mapping registers. This allows for flexibility in processing. The default settings

of these registers map each I2S input channel to its corresponding processing channel.

6.1.3

Configuration register C (addr 0x02)

FFX power output mode

FFX compensation pulse size register

Table 20. Channel input mapping

Bit

R/W

RST

Name

Description

R/W

C1IM

0: processing channel 1 receives left I2S input

1: processing channel 1 receives right I2S input

R/W

C2IM

0: processing channel 2 receives left I2S input

1: processing channel 2 receives right I2S input

OCRB

Reserved

CSZ3

CSZ2

CSZ1

CSZ0

OM1

OM0

10010111

Table 21. FFX power output mode

Bit

R/W

RST

Name

Description

R/W

OM0

The FFX power output mode selects the configuration

of the FFX output:

00: drop compensation

01: discrete output stage: tapered compensation

10: full-power mode

11: variable drop compensation (CSZx bits)

R/W

OM1

Table 22. FFX compensating pulse size

Bit

R/W

RST

Name

Description

R/W

CSZ0

When OM[1:0] = 11, this register determines the size of

the FFX compensating pulse from 0 to 15 clock periods:

0000: 0 ns (0 ticks) compensating pulse size

0001: 20 ns (1 tick) clock period compensating pulse

size

.....

1111: 300 ns (15 ticks) clock period compensating pulse

size

R/W

CSZ1

R/W

CSZ2

R/W

CSZ3

Obsolete

Product(s)

- Obsolete

Product(s)

STA380WS Datenblatt(PDF) 28 Page - STMicroelectronics

STA380WS Datenblatt(HTML) 28 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

Datenblatt Download

Link URL