1.E+01

1.E+02

1.E+03

1.E+04

1.E+05

1.E+06

1.E+07

1.E+08

1.E+09

1.E+10

1.E+11

1.E+12

200

1200

2200

3200

4200

5200

6200

50 %

Applied Voltage (VRMS)

54 years

36 years

20%

20%

VDE safety margin zone

Operating zone

TDDB (<1ppm fail rate)

Figure 8-5. Insulation Lifetime Projection Data

8.3 Power Supply Recommendations

To help provide reliable operation at data rates and supply voltages, a 0.1-μF bypass capacitor is recommended

at the input and output supply pins (VCC1 and VCC2). The capacitors must be placed as close to the supply

pins as possible. If only a single primary-side power supply is available in an application, isolated power can

be generated for the secondary-side with the help of a transformer driver such as Texas Instruments' SN6501

or SN6505A . For such applications, detailed power supply design and transformer selection recommendations

are available in SN6501 Transformer Driver for Isolated Power Supplies or SN6505 Low-Noise 1-A Transformer

Drivers for Isolated Power Supplies .

8.4 Layout

8.4.1 Layout Guidelines

A minimum of four layers is required to accomplish a low EMI PCB design (see Figure 8-6). Layer stacking must

be in the following order (top-to-bottom): high-speed signal layer, ground plane, power plane and low-frequency

signal layer.

• Routing the high-speed traces on the top layer avoids the use of vias (and the introduction of their

inductances) and allows for clean interconnects between the isolator and the transmitter and receiver circuits

of the data link.

• Placing a solid ground plane next to the high-speed signal layer establishes controlled impedance for

transmission line interconnects and provides an excellent low-inductance path for the return current flow.

• Placing the power plane next to the ground plane creates additional high-frequency bypass capacitance of

approximately 100 pF/in2.

• Routing the slower speed control signals on the bottom layer allows for greater flexibility as these signal links

usually have margin to tolerate discontinuities such as vias.

If an additional supply voltage plane or signal layer is needed, add a second power or ground plane system

to the stack to keep the planes symmetrical.. This makes the stack mechanically stable and prevents warping.

Also the power and ground plane of each power system can be placed closer together, thus increasing the

high-frequency bypass capacitance significantly.

For detailed layout recommendations, refer to the Digital Isolator Design Guide.

ISO7710

SLLSER9E – NOVEMBER 2016 – REVISED DECEMBER 2024

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