ST7FLCD1 datasheet(72/95 Pages) STMICROELECTRONICS

72 / 95 page

Display Data Channel Interfaces (DDC)

ST7FLCD1

72/95

DDC STATUS REGISTER 2 (DDCSR2)

Read Only

Reset Value: 0000 0000 (00h)

Bits [7:5] = Reserved. Forced to 0 by hardware.

Bit 4 = AF Acknowledge failure.

This bit is set by hardware when no acknowledge is returned. An interrupt is generated if ITE = 1. It

is cleared by software by reading the SR2 register or by hardware when the interface is disabled

(PE = 0).

The SCL line is not held low when AF = 1.

No acknowledge failure

Acknowledge failure

Bit 3 = STOPF Stop detection.

This bit is set by hardware when a Stop condition is detected on the bus after an acknowledge (if

ACK = 1). An interrupt is generated if ITE = 1. It is cleared by software by reading the SR2 register

or by hardware when the interface is disabled (PE = 0). The SCL line is not held low when STOPF

= 1.

No Stop condition detected

Stop condition detected

Bit 2 = Reserved. Forced to 0 by hardware.

Bit 1 = BERR Bus error.

This bit is set by hardware when the interface detects a misplaced Start or Stop condition. An

interrupt is generated if ITE = 1. It is cleared by software by reading the SR2 register or by hardware

when the interface is disabled (PE = 0).

The SCL line is not held low when BERR = 1.

No misplaced Start or Stop condition

Misplaced Start or Stop condition

Bit 0 = DDCIF DDC/CI address detected.

This bit is set by hardware when the DDC/CI address (6Eh/6Fh) is detected on the bus when

DDCIEN = 1. It is cleared by hardware when a Stop condition (STOPF = 1) is detected, or when the

interface is disabled (PE = 0).

No DDC/CI address detected on bus

DDC/CI address detected on bus

DDC DATA REGISTER (DDCDR)

Read / Write

Reset Value: 0000 0000 (00h)

765

432

STOPF

BERR

DDCIF

765

432

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