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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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ST7FLCD1 Datenblatt(PDF) 16 Page - STMicroelectronics |
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ST7FLCD1 Datenblatt(HTML) 16 Page - STMicroelectronics |
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16 / 95 page  Central Processing Unit (CPU) ST7FLCD1 16/95 CONDITION CODE REGISTER (CC) Read/Write Reset Value: 111x1XXX The 8-bit Condition Code register contains the interrupt mask and four flags resulting from the instruction just executed. This register can also be handled by the PUSH and POP instructions. These bits can be individually tested and/or controlled by specific instructions. Bit 4 = H Half carry. This bit is set by hardware when a carry occurs between bits 3 and 4 of the ALU during an ADD or ADC instruction. It is reset by hardware during the same instructions. 0: No half carry has occurred. 1: A half carry has occurred. This bit is tested using the JRH or JRNH instruction. The H bit is useful in BCD arithmetic subroutines. Note: Instruction Groups are defined in Table 5. Figure 5: CPU Registers 7 0 111 H I N Z C Accumulator X Index Register Y Index Register Stack Pointer Condition Code Register Program Counter 70 1C 11H I N Z Reset Value = Reset Vector @ FFFEh-FFFFh 70 70 70 0 7 15 8 PCH PCL 15 8 70 Reset Value = Stack Higher Address Reset Value = 1X 11X 1X X Reset Value = XXh Reset Value = XXh Reset Value = XXh X = Undefined Value |
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