ST7FLCD1 datasheet(32/95 Pages) STMICROELECTRONICS

32 / 95 page

Clocks & Low Power Modes

ST7FLCD1

32/95

Clocks & Low Power Modes

6.1

Clock System

6.1.1

General Description

The device requires a certain number of clock signals in order to operate. All clock signals are

derived from the root clock signal CkXT provided at the output of the "OSC" circuit (refer to

Figure 13). If a crystal oscillator or ceramic resonator is applied on pins OSCIN and OSCOUT, the

OSC operates in a crystal-controlled oscillator mode. An external clock signal can also be applied

on the OSCIN pin, putting the OSC in external clock mode operation.

The block diagram in Figure 13 shows the basic configuration of the clock system.

6.1.2

Crystal Oscillator Mode

In this mode, the root clock is generated by the on-chip oscillator controlled by an external parallel

fundamental-mode crystal oscillator or a ceramic resonator. General design precautions must be

followed to ensure maximum stability. Foot capacitors CL1 and CL2 must be adapted to match the

crystal oscillator or ceramic resonator. A 100-k

Ω resistor is internally connected between pins

OSCIN and OSCOUT.

Note:

If a Murata ceramic resonator is to be used, Murata recommends their CERALOCK® CSTCG-

series (fundamental type) with built-in CL1 and CL2 capacitors, such as:

- CSTCG24M0V51-R0 for 24-MHz external, 8-MHz internal clock operation

- CSTCG27M0V51-R0 for 27-MHz external, 9-MHz internal clock operation

No additional external capacitor is therefore needed with either model of this series.

6.1.3

External Clock Mode

In this mode, an external clock is provided on pin OSCIN, while pin OSCOUT is left open. The

signal is internally buffered before feeding the subsequent stages. There is the same emphasis on

stability of the external clock as in Crystal Oscillator mode.

Figure 13: Main Clock Generation

OSC

CkXT

OSC

CkXT

External

Clock

Crystal Oscillator Mode

External Clock Mode

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