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Datenblatt-Suchmaschine für elektronische Bauteile |
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Datenblatt-Suchmaschine für elektronische Bauteile |
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LAN9312 Datenblatt(PDF) 8 Page - SMSC Corporation |
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LAN9312 Datenblatt(HTML) 8 Page - SMSC Corporation |
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8 / 458 page  High Performance Two Port 10/100 Managed Ethernet Switch with 32-Bit Non-PCI CPU Interface Datasheet Revision 1.2 (04-08-08) 8 SMSC LAN9312 DATASHEET 14.2.4 EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 197 14.2.4.1 EEPROM Command Register (E2P_CMD) .................................................................................................................................................. 197 14.2.4.2 EEPROM Data Register (E2P_DATA).......................................................................................................................................................... 200 14.2.5 IEEE 1588 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 201 14.2.5.1 Port x 1588 Clock High-DWORD Receive Capture Register (1588_CLOCK_HI_RX_CAPTURE_x) .......................................................... 201 14.2.5.2 Port x 1588 Clock Low-DWORD Receive Capture Register (1588_CLOCK_LO_RX_CAPTURE_x) .......................................................... 202 14.2.5.3 Port x 1588 Sequence ID, Source UUID High-WORD Receive Capture Register (1588_SEQ_ID_SRC_UUID_HI_RX_CAPTURE_x)..... 203 14.2.5.4 Port x 1588 Source UUID Low-DWORD Receive Capture Register (1588_SRC_UUID_LO_RX_CAPTURE_x)........................................ 204 14.2.5.5 Port x 1588 Clock High-DWORD Transmit Capture Register (1588_CLOCK_HI_TX_CAPTURE_x).......................................................... 205 14.2.5.6 Port x 1588 Clock Low-DWORD Transmit Capture Register (1588_CLOCK_LO_TX_CAPTURE_x) ......................................................... 206 14.2.5.7 Port x 1588 Sequence ID, Source UUID High-WORD Transmit Capture Register (1588_SEQ_ID_SRC_UUID_HI_TX_CAPTURE_x) .... 207 14.2.5.8 Port x 1588 Source UUID Low-DWORD Transmit Capture Register (1588_SRC_UUID_LO_TX_CAPTURE_x) ....................................... 208 14.2.5.9 GPIO 8 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_8).................................................................. 209 14.2.5.10 GPIO 8 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_8) ................................................................. 210 14.2.5.11 GPIO 9 1588 Clock High-DWORD Capture Register (1588_CLOCK_HI_CAPTURE_GPIO_9).................................................................. 211 14.2.5.12 GPIO 9 1588 Clock Low-DWORD Capture Register (1588_CLOCK_LO_CAPTURE_GPIO_9) ................................................................. 212 14.2.5.13 1588 Clock High-DWORD Register (1588_CLOCK_HI)............................................................................................................................... 213 14.2.5.14 1588 Clock Low-DWORD Register (1588_CLOCK_LO) .............................................................................................................................. 214 14.2.5.15 1588 Clock Addend Register (1588_CLOCK_ADDEND) ............................................................................................................................. 215 14.2.5.16 1588 Clock Target High-DWORD Register (1588_CLOCK_TARGET_HI)................................................................................................... 216 14.2.5.17 1588 Clock Target Low-DWORD Register (1588_CLOCK_TARGET_LO) .................................................................................................. 217 14.2.5.18 1588 Clock Target Reload High-DWORD Register (1588_CLOCK_TARGET_RELOAD_HI) ..................................................................... 218 14.2.5.19 1588 Clock Target Reload/Add Low-DWORD Register (1588_CLOCK_TARGET_RELOAD_LO).............................................................. 219 14.2.5.20 1588 Auxiliary MAC Address High-WORD Register (1588_AUX_MAC_HI) ................................................................................................ 220 14.2.5.21 1588 Auxiliary MAC Address Low-DWORD Register (1588_AUX_MAC_LO) ............................................................................................. 221 14.2.5.22 1588 Configuration Register (1588_CONFIG).............................................................................................................................................. 222 14.2.5.23 1588 Interrupt Status and Enable Register (1588_INT_STS_EN)................................................................................................................ 226 14.2.5.24 1588 Command Register (1588_CMD) ........................................................................................................................................................ 228 14.2.6 Switch Fabric . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 229 14.2.6.1 Port 1 Manual Flow Control Register (MANUAL_FC_1)............................................................................................................................... 229 14.2.6.2 Port 2 Manual Flow Control Register (MANUAL_FC_2)............................................................................................................................... 231 14.2.6.3 Port 0(Host MAC) Manual Flow Control Register (MANUAL_FC_MII) ......................................................................................................... 233 14.2.6.4 Switch Fabric CSR Interface Data Register (SWITCH_CSR_DATA) ........................................................................................................... 235 14.2.6.5 Switch Fabric CSR Interface Command Register (SWITCH_CSR_CMD) ................................................................................................... 236 14.2.6.6 Switch Fabric MAC Address High Register (SWITCH_MAC_ADDRH) ........................................................................................................ 238 14.2.6.7 Switch Fabric MAC Address Low Register (SWITCH_MAC_ADDRL) ......................................................................................................... 239 14.2.6.8 Switch Fabric CSR Interface Direct Data Register (SWITCH_CSR_DIRECT_DATA) ................................................................................. 240 14.2.7 PHY Management Interface (PMI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 243 14.2.7.1 PHY Management Interface Data Register (PMI_DATA) ............................................................................................................................. 243 14.2.7.2 PHY Management Interface Access Register (PMI_ACCESS) .................................................................................................................... 244 14.2.8 Virtual PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 14.2.8.1 Virtual PHY Basic Control Register (VPHY_BASIC_CTRL) ......................................................................................................................... 246 14.2.8.2 Virtual PHY Basic Status Register (VPHY_BASIC_STATUS)...................................................................................................................... 248 14.2.8.3 Virtual PHY Identification MSB Register (VPHY_ID_MSB) .......................................................................................................................... 250 14.2.8.4 Virtual PHY Identification LSB Register (VPHY_ID_LSB) ............................................................................................................................ 251 14.2.8.5 Virtual PHY Auto-Negotiation Advertisement Register (VPHY_AN_ADV).................................................................................................... 252 14.2.8.6 Virtual PHY Auto-Negotiation Link Partner Base Page Ability Register (VPHY_AN_LP_BASE_ABILITY) .................................................. 254 14.2.8.7 Virtual PHY Auto-Negotiation Expansion Register (VPHY_AN_EXP) .......................................................................................................... 256 14.2.8.8 Virtual PHY Special Control/Status Register (VPHY_SPECIAL_CONTROL_STATUS) .............................................................................. 257 14.2.9 Miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 14.2.9.1 Chip ID and Revision (ID_REV).................................................................................................................................................................... 259 14.2.9.2 Byte Order Test Register (BYTE_TEST) ...................................................................................................................................................... 260 14.2.9.3 Hardware Configuration Register (HW_CFG)............................................................................................................................................... 261 14.2.9.4 Power Management Control Register (PMT_CTRL) .................................................................................................................................... 264 14.2.9.5 General Purpose Timer Configuration Register (GPT_CFG) ....................................................................................................................... 266 14.2.9.6 General Purpose Timer Count Register (GPT_CNT) ................................................................................................................................... 267 14.2.9.7 Free Running 25MHz Counter Register (FREE_RUN)................................................................................................................................. 268 14.2.9.8 Reset Control Register (RESET_CTL) ......................................................................................................................................................... 269 14.3 Host MAC Control and Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 270 14.3.1 Host MAC Control Register (HMAC_CR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 271 14.3.2 Host MAC Address High Register (HMAC_ADDRH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 274 14.3.3 Host MAC Address Low Register (HMAC_ADDRL) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 275 14.3.4 Host MAC Multicast Hash Table High Register (HMAC_HASHH) . . . . . . . . . . . . . . . . . . . . . . . 276 14.3.5 Host MAC Multicast Hash Table Low Register (HMAC_HASHL). . . . . . . . . . . . . . . . . . . . . . . . 277 14.3.6 Host MAC MII Access Register (HMAC_MII_ACC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 14.3.7 Host MAC MII Data Register (HMAC_MII_DATA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 279 14.3.8 Host MAC Flow Control Register (HMAC_FLOW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 280 14.3.9 Host MAC VLAN1 Tag Register (HMAC_VLAN1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 282 14.3.10 Host MAC VLAN2 Tag Register (HMAC_VLAN2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 14.3.11 Host MAC Wake-up Frame Filter Register (HMAC_WUFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . 284 14.3.12 Host MAC Wake-up Control and Status Register (HMAC_WUCSR) . . . . . . . . . . . . . . . . . . . . . 285 14.4 Ethernet PHY Control and Status Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 286 |
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