H8SXSLASH1663 datasheet(454/1158 Pages) RENESAS

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Section 8 Data Transfer Controller (DTC)

Rev.1.00 Jun. 07, 2006 Page 402 of 1102

REJ09B0294-0100

8.2.6

DTC Transfer Count Register B (CRB)

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in

block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1

every time data is transferred, and bit DTCEn (n = 15 to 0) corresponding to the activation source

is cleared and then an interrupt is requested to the CPU when the count reaches H'0000. The

transfer count is 1 when CRB = H'0001, 65,535 when CRB = H'FFFF, and 65,536 when CRB =

H'0000.

CRB is not available in normal and repeat modes and cannot be accessed directly by the CPU.

8.2.7

DTC enable registers A to E, G, and H

(DTCERA to DTCERE, DTCERG, and DTCERH)

DTCER which is comprised of eight registers, DTCERA to DTCERE, DTCERG, and DTCERH,

is a register that specifies DTC activation interrupt sources. The correspondence between interrupt

sources and DTCE bits is shown in table 8.1. Use bit manipulation instructions such as BSET and

BCLR to read or write a DTCE bit. If all interrupts are masked, multiple activation sources can be

set at one time (only at the initial setting) by writing data after executing a dummy read on the

relevant register.

Bit

Bit Name

Initial Value

R/W

DTCE15

R/W

DTCE14

R/W

DTCE13

R/W

DTCE12

R/W

DTCE11

R/W

DTCE10

R/W

DTCE9

R/W

DTCE8

R/W

Bit

Bit Name

Initial Value

R/W

DTCE7

R/W

DTCE6

R/W

DTCE5

R/W

DTCE4

R/W

DTCE3

R/W

DTCE2

R/W

DTCE1

R/W

DTCE0

R/W

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