H8SXSLASH1663R datasheet(399/1504 Pages) RENESAS

399 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 367 of 1468

REJ09B0412-0200

9.16

Bus Arbitration

This LSI has bus arbiters that arbitrate bus mastership operations (bus arbitration). This LSI

incorporates internal access and external access bus arbiters that can be used and controlled

independently. The internal bus arbiter handles the CPU, DTC, and DMAC accesses. The external

bus arbiter handles the external access by the CPU, DTC, DMAC, and EXDMAC, refresh, and

external bus release request (external bus master).

The bus arbiters determine priorities at the prescribed timing, and permit use of the bus by means

of the bus request acknowledge signal.

9.16.1

Operation

The bus arbiter detects the bus masters' bus request signals, and if the bus is requested, sends a bus

request acknowledge signal to the bus master. If there are bus requests from more than one bus

master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus

master receives the bus request acknowledge signal, it takes possession of the bus until that signal

is canceled.

The priority of the internal bus arbitration:

DMAC > DTC > CPU

The priority of the external bus arbitration:

Refresh > EXDMAC > External bus release request > External access by the CPU, DTC, or

DMAC

If the DMAC or DTC accesses continue, the CPU can be given priority over the DMAC or DTC

to execute the bus cycles alternatively between them by setting the IBCCS bit in BCR2. In this

case, the priority between the DMAC and DTC does not change. If an external bus release request,

an EXDMAC access, and a refresh cycle request continue, an external bus access by the CPU,

DTC, and DMAC can be given priority to execute the bus cycles alternatively between them by

setting the EBCCS bit in BCR2. In this case, the priorities among the refresh, EXDMAC, and

external bus release request do not change.

An internal bus access by internal bus masters and an external bus access by an external bus

release request, a refresh cycle, or an EXDMAC access can be executed in parallel.

H8SX/1663R Datenblatt(PDF) 399 Page - Renesas Technology Corp