H8SXSLASH1663R datasheet(403/1504 Pages) RENESAS

403 / 1504 page

Section 9 Bus Controller (BSC)

Rev. 2.00 Sep. 24, 2008 Page 371 of 1468

REJ09B0412-0200

9.17

Bus Controller Operation in Reset

In a reset, this LSI, including the bus controller, enters the reset state immediately, and any

executing bus cycle is aborted.

9.18

Usage Notes

(1)

Setting Registers

The BSC registers must be specified before accessing the external address space. In on-chip ROM

disabled mode, the BSC registers must be specified before accessing the external address space for

other than an instruction fetch access.

(2)

Mode Settings

The burst read-burst write mode of synchronous DRAM is not supported.

When setting the mode register of synchronous DRAM, the burst read-single write mode must be

selected and the burst length must be 1.

(3)

External Bus Release Function and All-Module-Clock-Stop Mode

In this LSI, if the ACSE bit in MSTPCRA is set to 1 and a SLEEP instruction is executed to enter

the sleep state after shutting off the clocks to all peripheral modules (MSTPCRA and MSTPCRB

= H'FFFFFFF) or allowing operation of the 8-bit timer module alone (MSTPCRA and MSTPCRB

= H'F[C to F]FFFFFF), the all-module-clock-stop mode is entered in which the clock for the bus

controller and I/O ports is also stopped. For details, see section 28, Power-Down Modes.

In this state, the external bus release function is halted. To use the external bus release function in

sleep mode, the ACSE bit in MSTPCRA must be cleared to 0. Conversely, if a SLEEP instruction

to place the chip in all-module-clock-stop mode is executed in the external bus released state, the

transition to all-module-clock-stop mode is deferred and performed until after the bus is

recovered.

(4)

External Bus Release Function and Software Standby Mode

In this LSI, internal bus master operation does not stop even while the bus is released, as long as

the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP

instruction to place the chip in software standby mode is executed while the external bus is

released, the transition to software standby mode is deferred and performed after the bus is

recovered.

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