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H8SX/1663R Datenblatt(PDF) 401 Page - Renesas Technology Corp

Teilenummer H8SX/1663R
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

H8SX/1663R Datenblatt(HTML) 401 Page - Renesas Technology Corp

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Section 9 Bus Controller (BSC)
Rev. 2.00 Sep. 24, 2008 Page 369 of 1468
REJ09B0412-0200
Note, however, that the bus cannot be transferred in the following cases.
• During transfer information read
• During the first data transfer
• During transfer information write back
The DTC releases the bus when the consecutive transfer cycles completed.
(3)
DMAC
The DMAC sends the internal bus arbiter a request for the bus when an activation request is
generated. When the DMAC accesses an external bus space, the DMAC first takes control of the
bus from the internal bus arbiter and then requests a bus to the external bus arbiter.
After the DMAC takes control of the bus, it may continue the transfer processing cycles or release
the bus at the end of every bus cycle depending on the conditions.
The DMAC continues transfers without releasing the bus in the following case:
• Between the read cycle in the dual-address mode and the write cycle corresponding to the read
cycle
If no bus master of a higher priority than the DMAC requests the bus and the IBCCS bit in BCR2
is cleared to 0, the DMAC continues transfers without releasing the bus in the following cases:
• During 1-block transfers in the block transfer mode
• During transfers in the burst mode
In other cases, the DMAC transfers the bus at the end of the bus cycle.
(4)
EXDMAC
The EXDMAC sends the external bus arbiter a request for the bus when an activation request is
generated. If an internal bus master accesses the external space, the bus is passed to the EXDMAC
when the bus master can release the bus. Some EXDMAC transfers are continued once it takes
control of the bus. Some EXDMAC transfers are divided and it releases the bus for each transfer
cycle.
• Transfers are continued without bus release between a read cycle and the subsequent write
cycle in dual address mode
• Transfers are continued without bus release in cluster transfer mode



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