H8SXSLASH1663R datasheet(419/1504 Pages) RENESAS

419 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 387 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

DTE

R/W

Data Transfer Enable

Enables/disables a data transfer for the corresponding

channel. When this bit is set to 1, it indicates that the

DMAC is in operation.

Setting this bit to 1 starts a transfer when the auto-

request is selected. When the on-chip module interrupt

or external request is selected, a transfer request after

setting this bit to 1 starts the transfer. While data is

being transferred, clearing this bit to 0 stops the

transfer.

In block transfer mode, if writing 0 to this bit while data is

being transferred, this bit is cleared to 0 after the current

1-block size data transfer.

If an event which stops (sustains) a transfer occurs

externally, this bit is automatically cleared to 0 to stop

the transfer.

Operating modes and transfer methods must not be

changed while this bit is set to 1.

0: Disables a data transfer

1: Enables a data transfer (DMA is in operation)

[Clearing conditions]

• When the specified total transfer size of transfers is

completed

• When a transfer is stopped by an overflow interrupt

by a repeat size end

• When a transfer is stopped by an overflow interrupt

by an extended repeat size end

• When a transfer is stopped by a transfer size error

interrupt

• When clearing this bit to 0 to stop a transfer

In block transfer mode, this bit changes after the current

block transfer.

• When an address error or an NMI interrupt is

requested

• In the reset state or hardware standby mode

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