H8SXSLASH1663R datasheet(422/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 390 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

DTIF

R/(W)* Data Transfer Interrupt Flag

Indicates that a transfer end interrupt by the transfer

counter has been requested.

0: A transfer end interrupt by the transfer counter has

not been requested

1: A transfer end interrupt by the transfer counter has

been requested

[Clearing conditions]

• When setting the DTE bit to 1

• When clearing to 0 after reading DTIF = 1

[Setting condition]

• When DTCR reaches 0 and the transfer is

completed

DTSZ1

DTSZ0

R/W

Data Access Size 1 and 0

Select the data access size for a transfer.

00: Byte size (eight bits)

01: Word size (16 bits)

10: Longword size (32 bits)

11: Setting prohibited

MDS1

MDS0

R/W

Transfer Mode Select 1 and 0

Select the transfer mode.

00: Normal transfer mode

01: Block transfer mode

10: Repeat transfer mode

11: Setting prohibited

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