H8SXSLASH1663R datasheet(423/1504 Pages) RENESAS

423 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 391 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

TSEIE

R/W

Transfer Size Error Interrupt Enable

Enables/disables a transfer size error interrupt.

When the next transfer is requested while this bit is set

to 1 and the contents of the transfer counter is less than

the size of data to be transferred at a single transfer

request, the DTE bit is cleared to 0. At this time, the

ESIF bit is set to 1 to indicate that a transfer size error

interrupt has been requested.

The sources of a transfer size error are as follows:

• In normal or repeat transfer mode, the total transfer

size set in DTCR is less than the data access size

• In block transfer mode, the total transfer size set in

DTCR is less than the block size

0: Disables a transfer size error interrupt request

1: Enables a transfer size error interrupt request



Reserved

This bit is always read as 0 and cannot be modified.

ESIE

R/W

Transfer Escape Interrupt Enable

Enables/disables a transfer escape end interrupt

request. When the ESIF bit is set to 1 with this bit set to

1, a transfer escape end interrupt is requested to the

CPU or DTC. The transfer end interrupt request is

cleared by clearing this bit or the ESIF bit to 0.

0: Disables a transfer escape end interrupt

1: Enables a transfer escape end interrupt

DTIE

R/W

Data Transfer End Interrupt Enable

Enables/disables a transfer end interrupt request by the

transfer counter. When the DTIF bit is set to 1 with this

bit set to 1, a transfer end interrupt is requested to the

CPU or DTC. The transfer end interrupt request is

cleared by clearing this bit or the DTIF bit to 0.

0: Disables a transfer end interrupt

1: Enables a transfer end interrupt

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