H8SXSLASH1663R datasheet(420/1504 Pages) RENESAS

420 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 388 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

DACKE

R/W

DACK Signal Output Enable

Enables/disables the

DACK signal output in single

address mode. This bit is ignored in dual address mode.

0: Disables

DACK signal output

1: Enables

DACK signal output

TENDE

R/W

TEND Signal Output Enable

Enables/disables the

TEND signal output.

0: Disables

TEND signal output

1: Enables

TEND signal output



R/W

Reserved

Initial value should not be changed.

DREQS

R/W

DREQ Select

Selects whether a low level or the falling edge of the

DREQ signal used in external request mode is detected.

0: Low level detection

1: Falling edge detection (the first transfer after a

transfer enabled is detected on a low level)

NRD

R/W

Next Request Delay

Selects the accepting timing of the next transfer request.

0: Starts accepting the next transfer request after

completion of the current transfer

1: Starts accepting the next transfer request one cycle

of B

φ after completion of the current transfer

25, 24



All 0

Reserved

These bits are always read as 0 and cannot be

modified.

ACT

Active State

Indicates the operating state for the channel.

0: Waiting for a transfer request or a transfer disabled

state by clearing the DTE bit to 0

1: Active state

22 to 20



All 0

Reserved

These bits are always read as 0 and cannot be

modified.

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