H8SXSLASH1663R datasheet(428/1504 Pages) RENESAS

428 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 396 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

19, 18



All 0

Reserved

These bits are always read as 0 and cannot be

modified.

DAT1

DAT0

R/W

Destination Address Update Mode 1 and 0

Select the update method of the destination address

(DDAR). When DDAR is not specified as the transfer

destination in single address mode, this bit is ignored.

00: Destination address is fixed

01: Destination address is updated by adding the offset

10: Destination address is updated by adding 1, 2, or 4

according to the data access size

11: Destination address is updated by subtracting 1, 2,

or 4 according to the data access size

SARIE

R/W

Interrupt Enable for Source Address Extended Area

Overflow

Enables/disables an interrupt request for an extended

area overflow on the source address.

When an extended repeat area overflow on the source

address occurs while this bit is set to 1, the DTE bit in

DMDR is cleared to 0. At this time, the ESIF bit in

DMDR is set to 1 to indicate an interrupt by an extended

repeat area overflow on the source address is

requested.

When block transfer mode is used with the extended

repeat area function, an interrupt is requested after

completion of a 1-block size transfer. When setting the

DTE bit in DMDR of the channel for which a transfer has

been stopped to 1, the transfer is resumed from the

state when the transfer is stopped.

When the extended repeat area is not specified, this bit

is ignored.

0: Disables an interrupt request for an extended area

overflow on the source address

1: Enables an interrupt request for an extended area

overflow on the source address

14, 13



All 0

Reserved

These bits are always read as 0 and cannot be

modified.

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