H8SXSLASH1663R datasheet(430/1504 Pages) RENESAS

Teilenummer	H8SX/1663R

Bauteilbeschribung	Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series

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Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 398 of 1468

REJ09B0412-0200

Bit

Bit Name

Initial

Value

R/W

Description

DARA4

DARA3

DARA2

DARA1

DARA0

R/W

Destination Address Extended Repeat Area

Specify the extended repeat area on the destination

address (DDAR). With the extended repeat area, the

specified lower address bits are updated and the

remaining upper address bits are fixed. The extended

repeat area size is specified from four bytes to 128

Mbytes in units of byte and a power of 2.

When the lower address is overflowed from the

extended repeat area by address update, the address

becomes the start address and the end address of the

area for address addition and subtraction, respectively.

When an overflow in the extended repeat area occurs

with the DARIE bit set to 1, an interrupt can be

requested. Table 10.3 shows the settings and areas of

the extended repeat area.

H8SX/1663R Datenblatt(PDF) 430 Page - Renesas Technology Corp