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H8SX/1663R Datenblatt(PDF) 427 Page - Renesas Technology Corp |
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H8SX/1663R Datenblatt(HTML) 427 Page - Renesas Technology Corp |
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427 / 1504 page ![]() Section 10 DMA Controller (DMAC) Rev. 2.00 Sep. 24, 2008 Page 395 of 1468 REJ09B0412-0200 Bit Bit Name Initial Value R/W Description 26 RPTIE 0 R/W Repeat Size End Interrupt Enable Enables/disables a repeat size end interrupt request. In repeat transfer mode, when the next transfer is requested after completion of a 1-repeat-size data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. Even when the repeat area is not specified (ARS1 = 1 and ARS0 = 0), a repeat size end interrupt after a 1-block data transfer can be requested. In addition, in block transfer mode, when the next transfer is requested after 1-block data transfer while this bit is set to 1, the DTE bit in DMDR is cleared to 0. At this time, the ESIF bit in DMDR is set to 1 to indicate that a repeat size end interrupt is requested. 0: Disables a repeat size end interrupt 1: Enables a repeat size end interrupt 25 24 ARS1 ARS0 0 0 R/W R/W Area Select 1 and 0 Specify the block area or repeat area in block or repeat transfer mode. 00: Specify the block area or repeat area on the source address 01: Specify the block area or repeat area on the destination address 10: Do not specify the block area or repeat area 11: Setting prohibited 23, 22 All 0 R Reserved These bits are always read as 0 and cannot be modified. 21 20 SAT1 SAT0 0 0 R/W R/W Source Address Update Mode 1 and 0 Select the update method of the source address (DSAR). When DSAR is not specified as the transfer source in single address mode, this bit is ignored. 00: Source address is fixed 01: Source address is updated by adding the offset 10: Source address is updated by adding 1, 2, or 4 according to the data access size 11: Source address is updated by subtracting 1, 2, or 4 according to the data access size |
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