H8SXSLASH1663R datasheet(426/1504 Pages) RENESAS

426 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 394 of 1468

REJ09B0412-0200

10.3.7

DMA Address Control Register (DACR)

DACR specifies the operating mode and transfer method.

AMS

R/W

DIRS

R/W



ARS0

R/W

RPTIE

R/W

ARS1

R/W

Bit

Bit Name

Initial Value

R/W



SAT1

R/W

SAT0

R/W



DAT0

R/W



DAT1

R/W

Bit

Bit Name

Initial Value

R/W

SARIE

R/W



SARA4

R/W

SARA3

R/W

SARA0

R/W

SARA2

R/W

SARA1

R/W

Bit

Bit Name

Initial Value

R/W

DARIE

R/W



DARA4

R/W

DARA3

R/W

DARA0

R/W

DARA2

R/W

DARA1

R/W

Bit

Bit Name

Initial Value

R/W

Bit

Bit Name

Initial

Value

R/W

Description

AMS

R/W

Address Mode Select

Selects address mode from single or dual address

mode. In single address mode, the

DACK pin is enabled

according to the DACKE bit.

0: Dual address mode

1: Single address mode

DIRS

R/W

Single Address Direction Select

Specifies the data transfer direction in single address

mode. This bit s ignored in dual address mode.

0: Specifies DSAR as source address

1: Specifies DDAR as destination address

29 to 27



All 0

Reserved

These bits are always read as 0 and cannot be

modified.

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