H8SXSLASH1663R datasheet(434/1504 Pages) RENESAS

434 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 402 of 1468

REJ09B0412-0200

10.5

Operations

10.5.1

Address Modes

(1)

Dual Address Mode

In dual address mode, the transfer source address is specified in DSAR and the transfer destination

address is specified in DDAR. A transfer at a time is performed in two bus cycles (when the data

bus width is less than the data access size or the access address is not aligned with the boundary of

the data access size, the number of bus cycles are needed more than two because one bus cycle is

divided into multiple bus cycles).

In the first bus cycle, data at the transfer source address is read and in the next cycle, the read data

is written to the transfer destination address.

The read and write cycles are not separated. Other bus cycles (bus cycle by other bus masters,

refresh cycle, and external bus release cycle) are not generated between read and write cycles.

The

TEND signal output is enabled or disabled by the TENDE bit in DMDR. The TEND signal is

output in two bus cycles. When an idle cycle is inserted before the bus cycle, the

TEND signal is

also output in the idle cycle. The

DACK signal is not output.

Figure 10.2 shows an example of the signal timing in dual address mode and figure 10.3 shows the

operation in dual address mode.

Address bus

TEND

DMA read

cycle

DMA write

cycle

DSAR

DDAR

Figure 10.2 Example of Signal Timing in Dual Address Mode

H8SX/1663R Datenblatt(PDF) 434 Page - Renesas Technology Corp