H8SXSLASH1663R datasheet(457/1504 Pages) RENESAS

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Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 425 of 1468

REJ09B0412-0200

(5)

DTE Bit in DMDR

Although the DTE bit in DMDR enables or disables data transfer by the CPU write access, it is

automatically cleared to 0 according to the DMA transfer state by the DMAC.

The conditions for clearing the DTE bit by the DMAC are as follows:

• When the total size of transfers is completed

• When a transfer is completed by a transfer size error interrupt

• When a transfer is completed by a repeat size end interrupt

• When a transfer is completed by an extended repeat area overflow interrupt

• When a transfer is stopped by an NMI interrupt

• When a transfer is stopped by and address error

• Reset state

• Hardware standby mode

• When a transfer is stopped by writing 0 to the DTE bit

Writing to the registers for the channels when the corresponding DTE bit is set to 1 is prohibited

(except for the DTE bit). When changing the register settings after writing 0 to the DTE bit,

confirm that the DTE bit has been cleared to 0.

Figure 10.21 show the procedure for changing the register settings for the channel being

transferred.

Read DTE bit

Write 0 to DTE bit

Change register settings

DTE = 0?

[1]

[2]

[3]

[4]

Yes

Changing register settings

of channel during operation

End of changing

[1] Write 0 to the DTE bit in DMDR.

[2] Read the DTE bit.

[3] Confirm that DTE = 0. DTE = 1

indicates that DMA is transferring.

[4] Write the desired values to the

registers.

Figure 10.21 Procedure for Changing Register Setting For Channel being Transferred

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