H8SXSLASH1663R datasheet(453/1504 Pages) RENESAS

453 / 1504 page

Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 421 of 1468

REJ09B0412-0200

When a transfer starts, the transfer source address is added to the offset every time data is

transferred. The transfer data is written to the destination continuous addresses. When data 4 is

transferred meaning that the repeat size of transfers is completed, the transfer source address

returns to the transfer start address (address of data 1 on the transfer source) and a repeat size end

interrupt is requested. While this interrupt stops the transfer temporarily, the contents of DSAR are

written to the address of data 5 by the CPU (when the data access size is longword, write the data

1 address + 4). When the DTE bit in DMDR is set to 1, the transfer is resumed from the state when

the transfer is stopped. Accordingly, operations are repeated and the transfer source data is

transposed to the destination area (XY conversion).

Figure 10.20 shows a flowchart of the XY conversion.

: User operation

: DMAC operation

Start

Set address and transfer count

Set repeat transfer mode

Set DTE bit to 1

Receives transfer request

Transfers data

Decrements transfer count

and repeat size

Enable repeat escape interrupt

Set transfer source address + 4

Initializes transfer source address

Generates repeat size end

interrupt request

Transfer count = 0?

Repeat size = 0?

End

Yes

(Longword transfer)

Figure 10.20 XY Conversion Flowchart Using Offset Addition in Repeat Transfer Mode

H8SX/1663R Datenblatt(PDF) 453 Page - Renesas Technology Corp