H8SXSLASH1663R datasheet(455/1504 Pages) RENESAS

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Section 10 DMA Controller (DMAC)

Rev. 2.00 Sep. 24, 2008 Page 423 of 1468

REJ09B0412-0200

In block or repeat transfer mode, when the block or repeat size of data transfers is completed while

the block or repeat area is specified to the source address side, the source address returns to the

transfer start address and is not affected by the address update.

When the extended repeat area is specified to the source address side, operation follows the

setting. The upper address bits are fixed and is not affected by the address update.

While data is being transferred, DSAR must be accessed in longwords. If the upper word and

lower word are read separately, incorrect data may be read from since the contents of DSAR

during the transfer may be updated regardless of the access by the CPU. Moreover, DSAR for the

channel being transferred must not be written to.

(2)

DMA Destination Address Register

When the transfer destination address set in DDAR is accessed, the contents of DDAR are output

and then are updated to the next address.

The increment or decrement can be specified by bits DAT1 and DAT0 in DACR. When DAT1

and DAT0 = B'00, the address is fixed. When DAT1 and DAT0 = B'01, the address is added with

the offset. When DAT1 and DAT0 = B'10, the address is incremented. When DAT1 and DAT0 =

B'11, the address is decremented. The incrementing or decrementing size depends on the data

access size.

The data access size is specified by bits DTSZ1 and DTSZ0 in DMDR. When DTSZ1 and DTSZ0

= B'00, the data access size is byte and the address is incremented or decremented by 1. When

DTSZ1 and DTSZ0 = B'01, the data access size is word and the address is incremented or

decremented by 2. When DTSZ1 and DTSZ0 = B'10, the data access size is longword and the

address is incremented or decremented by 4. Even if the access data size of the destination address

is word or longword, when the destination address is not aligned with the word or longword

boundary, the write bus cycle is divided into byte and word cycles. While one word or one

longword of data is being written, the incrementing or decrementing size is changing according to

the actual data access size, for example, +1 or +2 for byte or word data. After the one word or one

longword of data is written, the address when the write cycle is started is incremented or

decremented by the value according to bits SAT1 and SAT0.

In block or repeat transfer mode, when the block or repeat size of data transfers is completed while

the block or repeat area is specified to the destination address side, the destination address returns

to the transfer start address and is not affected by the address update.

When the extended repeat area is specified to the destination address side, operation follows the

setting. The upper address bits are fixed and is not affected by the address update.

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