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H8SX/1663R Datenblatt(PDF) 570 Page - Renesas Technology Corp

Teilenummer H8SX/1663R
Bauteilbeschribung  Renesas 32-Bit CISC Microcomputer H8SX Family / H8SX/1600 Series
PDF  1504 Pages
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Hersteller  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
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H8SX/1663R Datenblatt(HTML) 570 Page - Renesas Technology Corp

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Section 11 EXDMA Controller (EXDMAC)
Rev. 2.00 Sep. 24, 2008 Page 538 of 1468
REJ09B0412-0200
(2)
EDREQ Pin Falling Edge Activation Timing
Figure 11.62 shows an example of cluster transfer mode transfer activated by the
EDREQ pin
falling edge.
EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the
DTE bit write cycle.
When a low level is sampled at the
EDREQ pin while acceptance of a transfer request via the
EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated
within the EXDMAC, the request is cleared, and
EDREQ pin high level sampling for edge sensing
is started. If
EDREQ pin high level sampling is completed by the end of the last cluster write
cycle, acceptance resumes after the end of the write cycle, and
EDREQ pin low level sampling is
performed again. This sequence of operations is repeated until the end of the transfer.
Bus release
One cluster transfer
B
φ
EDREQ
Address bus
Channel
EXDMA control
Transfer destination
Request
[1]
[1]
[2] [5]
[3] [6]
[4] [7]
Acceptance after transfer enabling;
EDREQ pin low level is sampled at rise of Bφ, and request is held.
Request is cleared at end of next bus cycle, and activation is started in EXDMAC.
EXDMA cycle starts;
EDREQ pin high level sampling is started at rise of Bφ.
When
EDREQ pin high level has been sampled, acceptance is resumed after completion of write cycle.
(As in [1],
EDREQ pin low level is sampled at rise of Bφ, and request is held.)
[2]
[3]
[4]
[5]
[6]
[7]
Request
Transfer source
Transfer destination
Consecutive write
Minimum 3 cycles
Request clearance period
Minimum 3 cycles
Request clearance period
Transfer source
Consecutive read
Bus release
One cluster transfer
Consecutive write
Consecutive read
Figure 11.62 Example of Cluster Transfer Mode Transfer Activated
by
EDREQ Pin Falling Edge



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