H8SXSLASH1663R datasheet(571/1504 Pages) RENESAS

571 / 1504 page

Section 11 EXDMA Controller (EXDMAC)

Rev. 2.00 Sep. 24, 2008 Page 539 of 1468

REJ09B0412-0200

(3)

EDREQ Pin Low Level Activation Timing

Figure 11.63 shows an example of cluster transfer mode transfer activated by the

EDREQ pin low

level.

EDREQ pin sampling is performed in each cycle starting at the next rise of Bφ after the end of the

DTE bit write cycle.

When a low level is sampled at the

EDREQ pin while acceptance of a transfer request via the

EDREQ pin is possible, the request is held within the EXDMAC. Then when activation is initiated

within the EXDMAC, the request is cleared. At the end of the last cluster write cycle, acceptance

resumes and

EDREQ pin low level sampling is performed again. This sequence of operations is

repeated until the end of the transfer.

When NRD bit = 0 in EDMDR, acceptance resumes at the end of the last cluster write cycle and

EDREQ pin low level sampling is performed again. This sequence of operations is repeated until

the end of the transfer.

When NRD bit = 1 in EDMDR, acceptance resumes after one cycle from the end of the last cluster

write cycle, and

EDREQ pin low level sampling is performed again. This sequence of operations

is repeated until the end of the transfer.

Bus release

One cluster transfer

EDREQ

Address bus

Channel

EXDMA control

[1]

[2] [5]

[3] [6]

[4] [7]

Acceptance after transfer enabling;

EDREQ pin low level is sampled at rise of Bφ, and request is held.

Request is cleared at the end of next bus cycle, and activation is started in EXDMAC.

EXDMA cycle stars.

Acceptance is resumed after completion of wite cycle.

(As in [1],

EDREQ pin low level is sampled at rise of Bφ, and request is held.)

[2]

[3]

[4]

[5]

[6]

[7]

Transfer source

Transfer destination

Consecutive read

Consecutive write

Request clearance period

Request

Minimum 3 cycles

Figure 11.63 Example of Cluster Transfer Mode Transfer Activated

EDREQ Pin Low Level

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