LT1952IGN datasheet(9/24 Pages) LINER

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LT1952/LT1952-1

19521fd

TIMING DIAGRAM

BLOCK DIAGRAM

1952 F01

tDELAY: PROGRAMMABLE SYNCHRONOUS DELAY

FAULTS TRIGGERING SOFT-START

VIN < 8.75V

SD_VSEC < 1.32V (UVLO)

OC > 107mV (OVERCURRENT)

SOFT-START LATCH RESET:

VIN > 14.25V (> 8.75V IF LATCH SET BY OC)

AND

SD_VSEC > 1.32V

AND

OC < 107mV

AND

SS_MAXDC < 0.45V

SOFT-START

LATCH SET

SOUT

OUT

SS_MAXDC

0.8V (ACTIVE THRESHOLD)

0.45V (RESET THRESHOLD)

0.2V

VREF

>90%

–

SOURCE

2.5mA

2.5V

1.23V

(100 TO 500)kHz

OSC

(TYPICAL 200kHz)

IHYST

10μA SD_VSEC = 1.32V

0μA SD_VSEC > 1.32V

SD_VSEC

ROSC

SYNC

1.32V

1.23V

ADAPTIVE

MAXIMUM

DUTY CYCLE

CLAMP

(LINEAR)

SLOPE COMP

8μA 0% DC

35μA 80% DC

RAMP

BLANK

COMP

GND

BLANK

DELAY

VREF

VIN

SS_MAXDC

SOFT-START CONTROL

OUT

16 SOUT

PGND

ISENSE

11 OC

DRIVER

50mA

12V

13V

0.45V

1952 BD

–

(VOLTAGE)

ERROR AMPLIFIER

107mV

0mV TO 220mV

DELAY

VINON

VINOFF

LT1952

ISTART = 460μA

VIN ON = 14.25V

VIN OFF = 8.75V

LT1952-1

ISTART = 400μA

VIN ON = 7.75V

VIN OFF = 6.5V

START-UP

INPUT CURRENT (ISTART)

–

SENSE

CURRENT

OVER

CURRENT

Figure 1. Timing Diagram

Figure 2. Block Diagram

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