ATmega162 datasheet(97/324 Pages) ATMEL

97 / 324 page

2513K–AVR–07/09

ATmega162/V

has lower maximum operation frequency than single slope operation. However, due to the sym-

metric feature of the dual-slope PWM modes, these modes are preferred for motor control

applications.

The PWM resolution for the phase correct PWM mode is fixed to eight bits. In phase correct

PWM mode the counter is incremented until the counter value matches MAX. When the counter

reaches MAX, it changes the count direction. The TCNT0 value will be equal to MAX for one

timer clock cycle. The timing diagram for the phase correct PWM mode is shown on Figure 39.

The TCNT0 value is in the timing diagram shown as a histogram for illustrating the dual-slope

operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal

line marks on the TCNT0 slopes represent compare matches between OCR0 and TCNT0.

Figure 39. Phase Correct PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches BOTTOM. The

Interrupt Flag can be used to generate an interrupt each time the counter reaches the BOTTOM

value.

In phase correct PWM mode, the compare unit allows generation of PWM waveforms on the

OC0 pin. Setting the COM01:0 bits to two will produce a non-inverted PWM. An inverted PWM

output can be generated by setting the COM01:0 to three (See Table 50 on page 101). The

actual OC0 value will only be visible on the port pin if the data direction for the port pin is set as

output. The PWM waveform is generated by clearing (or setting) the OC0 Register at the Com-

pare Match between OCR0 and TCNT0 when the counter increments, and setting (or clearing)

the OC0 Register at Compare Match between OCR0 and TCNT0 when the counter decrements.

The PWM frequency for the output when using phase correct PWM can be calculated by the fol-

lowing equation:

The N variable represents the prescale factor (1, 8, 64, 256, or 1024).

TOVn Interrupt Flag Set

OCn Interrupt Flag Set

TCNTn

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Update

fOCnPCPWM

clk_I/O

N 510

⋅

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ATmega162 Datenblatt(PDF) 97 Page - ATMEL Corporation