MPC8536BVTATH datasheet(115/128 Pages) FREESCALE

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Power Supply Design and Sequencing

MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

115

3.2

Power Supply Design and Sequencing

3.2.1

PLL Power Supply Filtering

Each of the PLLs listed above is provided with power through independent power supply pins (AVDD_PLAT, AVDD_CORE,

AVDD_PCI, AVDD_LBIU, and AVDD_SRDS respectively). The AVDD level should always be equivalent to VDD, and

preferably these voltages will be derived directly from VDD through a low frequency filter scheme such as the following.

There are a number of ways to reliably provide power to the PLLs, but the recommended solution is to provide independent

filter circuits per PLL power supply as illustrated in Figure 75, one to each of the AVDD pins. By providing independent filters

to each PLL the opportunity to cause noise injection from one PLL to the other is reduced.

This circuit is intended to filter noise in the PLLs resonant frequency range from a 500 kHz to 10 MHz range. It should be built

with surface mount capacitors with minimum Effective Series Inductance (ESL). Consistent with the recommendations of Dr.

Howard Johnson in High Speed Digital Design: A Handbook of Black Magic (Prentice Hall, 1993), multiple small capacitors

of equal value are recommended over a single large value capacitor.

Each circuit should be placed as close as possible to the specific AVDD pin being supplied to minimize noise coupled from

nearby circuits. It should be possible to route directly from the capacitors to the AVDD pin, which is on the periphery of 783

FC-PBGA the footprint, without the inductance of vias.

Figure 75 shows the PLL power supply filter Circuit.

Figure 75. MPC8536E PLL Power Supply Filter Circuit

The AVDD_SRDSn signals provides power for the analog portions of the SerDes PLL. To ensure stability of the internal clock,

the power supplied to the PLL is filtered using a circuit similar to the one shown in following Figure 76. For maximum

effectiveness, the filter circuit is placed as closely as possible to the AVDD_SRDSn balls to ensure it filters out as much noise

as possible. The ground connection should be near the AVDD_SRDSn balls. The 0.003-µF capacitor is closest to the balls,

followed by the 1-µF capacitor, and finally the 1 ohm resistor to the board supply plane. The capacitors are connected from

AVDD_SRDSn to the ground plane. Use ceramic chip capacitors with the highest possible self-resonant frequency. All traces

should be kept short, wide and direct.

Figure 76. SerDes PLL Power Supply Filter Circuit

Note the following:

•AVDD should be a filtered version of SVDD.

•

Signals on the SerDes interface are fed from the XVDD power plane.

VDD

AVDD

2.2 µF

GND

Low ESL Surface Mount Capacitors

2.2 µF 1

0.003 µF

GND

1.0

AVDD - SRDS

1. An 0805 sized capacitor is recommended for system initial bring-up

SnVDD

2.2 µF 1

MPC8536BVTATH Datenblatt(PDF) 115 Page - Freescale Semiconductor, Inc

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