MPC8536BVTATH datasheet(117/128 Pages) FREESCALE

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Pull-Up and Pull-Down Resistor Requirements

MPC8536E PowerQUICC™ III Integrated Processor Hardware Specifications, Rev. 2

Freescale Semiconductor

117

3.7

Pull-Up and Pull-Down Resistor Requirements

The MPC8536E requires weak pull-up resistors (2–10 k

Ω is recommended) on open drain type pins including I2C pins and

MPIC interrupt pins.

Correct operation of the JTAG interface requires configuration of a group of system control pins as demonstrated in Figure 78.

Care must be taken to ensure that these pins are maintained at a valid deasserted state under normal operating conditions as most

have asynchronous behavior and spurious assertion will give unpredictable results.

The following pins must NOT be pulled down during power-on reset: TSEC1_TXD[3], HRESET_REQ,

TRIG_OUT/READY/QUIESCE, MSRCID[2:4], ASLEEP. The UART_SOUT[0:1] and TEST_SEL pins must be set to a

proper state during POR configuration. Please refer to the pinlist table (see Table 62) of the individual device for more details.

See the PCI 2.2 specification for all pull-ups required for PCI.

3.8

Output Buffer DC Impedance

The MPC8536E drivers are characterized over process, voltage, and temperature. For all buses, the driver is a push-pull

single-ended driver type (open drain for I

2C).

To measure Z0 for the single-ended drivers, an external resistor is connected from the chip pad to OVDD or GND. Then, the

value of each resistor is varied until the pad voltage is OVDD/2 (see Figure 77). The output impedance is the average of two

components, the resistances of the pull-up and pull-down devices. When data is held high, SW1 is closed (SW2 is open) and

RP is trimmed until the voltage at the pad equals OVDD/2. RP then becomes the resistance of the pull-up devices. RP and RN

are designed to be close to each other in value. Then, Z0 = (RP + RN)/2.

Figure 77. Driver Impedance Measurement

Table 81 summarizes the signal impedance targets. The driver impedances are targeted at minimum VDD, nominal OVDD,

105

°C.

OVDD

OGND

Pad

Data

SW1

SW2

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