TMS320C6720RFP300 datasheet(86/118 Pages) TI

86 / 118 page

TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720

Floating-Point Digital Signal Processors

SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008

www.ti.com

Table 4-28. General Timing Requirements for SPIx Slave Modes(1)

NO.

MIN

MAX UNIT

greater of 8P or

tc(SPC)S

Cycle Time, SPIx_CLK, All Slave Modes

256P

100 ns

greater of 4P or

tw(SPCH)S

Pulse Width High, SPIx_CLK, All Slave Modes

45 ns

greater of 4P or

tw(SPCL)S

Pulse Width Low, SPIx_CLK, All Slave Modes

45 ns

Polarity = 0, Phase = 0,

to SPIx_CLK rising

Setup time, transmit data

Polarity = 0, Phase = 1,

written to SPI and output

to SPIx_CLK rising

tsu(SOMI_SPC)S

onto SPIx_SOMI pin before

Polarity = 1, Phase = 0,

initial clock edge from

to SPIx_CLK falling

master.(2)(3)

Polarity = 1, Phase = 1,

to SPIx_CLK falling

Polarity = 0, Phase = 0,

2P + 15

from SPIx_CLK rising

Polarity = 0, Phase = 1,

2P + 15

Delay, subsequent bits

from SPIx_CLK falling

td(SPC_SOMI)S

valid on SPIx_SOMI after

Polarity = 1, Phase = 0,

transmit edge of SPIx_CLK

2P + 15

from SPIx_CLK falling

Polarity = 1, Phase = 1,

2P + 15

from SPIx_CLK rising

Polarity = 0, Phase = 0,

0.5tc(SPC)S – 10

from SPIx_CLK falling

Polarity = 0, Phase = 1,

Output hold time,

0.5tc(SPC)S – 10

from SPIx_CLK rising

SPIx_SOMI valid after

toh(SPC_SOMI)S

receive edge of SPIxCLK,

Polarity = 1, Phase = 0,

0.5tc(SPC)S – 10

except for final bit(4)

from SPIx_CLK rising

Polarity = 1, Phase = 1,

0.5tc(SPC)S – 10

from SPIx_CLK falling

Polarity = 0, Phase = 0,

0.5P + 15

to SPIx_CLK falling

Polarity = 0, Phase = 1,

0.5P + 15

Input Setup Time,

to SPIx_CLK rising

tsu(SIMO_SPC)S

SPIx_SIMO valid before

Polarity = 1, Phase = 0,

receive edge of SPIx_CLK

0.5P + 15

to SPIx_CLK rising

Polarity = 1, Phase = 1,

0.5P + 15

to SPIx_CLK falling

Polarity = 0, Phase = 0,

0.5P + 5

from SPIx_CLK falling

Polarity = 0, Phase = 1,

0.5P + 5

Input Hold Time,

from SPIx_CLK rising

tih(SPC_SIMO)S

SPIx_SIMO valid after

Polarity = 1, Phase = 0,

receive edge of SPIx_CLK

0.5P + 5

from SPIx_CLK rising

Polarity = 1, Phase = 1,

0.5P + 5

from SPIx_CLK falling

(1)

P = SYSCLK2 period

(2)

First bit may be MSB or LSB depending upon SPI configuration. SO(0) refers to first bit and SO(n) refers to last bit output on

SPIx_SOMI. SI(0) refers to the first bit input and SI(n) refers to the last bit input on SPIx_SIMO.

(3)

Measured from the termination of the write of new data to the SPI module, as evidenced by new output data appearing on the

SPIx_SOMI pin. In analyzing throughput requirements, additional internal bus cycles must be accounted for to allow data to be written to

the SPI module by either the DSP CPU or the dMAX.

(4)

The final data bit will be held on the SPIx_SOMI pin until the SPIDAT0 or SPIDAT1 register is written with new data.

Peripheral and Electrical Specifications

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