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TMS320C6720RFP300 Datenblatt(PDF) 97 Page - Texas Instruments

Teilenummer TMS320C6720RFP300
Bauteilbeschribung  Floating-Point Digital Signal Processors
PDF  118 Pages
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TMS320C6720RFP300 Datenblatt(HTML) 97 Page - Texas Instruments

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4.15.3 I2C Electrical Data/Timing
4.15.3.1 Inter-Integrated Circuit (I2C) Timing
TMS320C6727B, TMS320C6726B, TMS320C6722B, TMS320C6720
Floating-Point Digital Signal Processors
www.ti.com
SPRS370E – SEPTEMBER 2006 – REVISED JULY 2008
Table 4-36 and Table 4-37 assume testing over recommended operating conditions (see Figure 4-38 and
Figure 4-39).
Table 4-36. I2C Input Timing Requirements
NO.
MIN
MAX
UNIT
Standard Mode
10
1
tc(SCL)
Cycle time, I2Cx_SCL
µs
Fast Mode
2.5
Standard Mode
4.7
Setup time, I2Cx_SCL high before I2Cx_SDA
2
tsu(SCLH-SDAL)
µs
low
Fast Mode
0.6
Standard Mode
4
3
th(SCLL-SDAL)
Hold time, I2Cx_SCL low after I2Cx_SDA low
µs
Fast Mode
0.6
Standard Mode
4.7
4
tw(SCLL)
Pulse duration, I2Cx_SCL low
µs
Fast Mode
1.3
Standard Mode
4
5
tw(SCLH)
Pulse duration, I2Cx_SCL high
µs
Fast Mode
0.6
Standard Mode
250
6
tsu(SDA-SCLH)
Setup time, I2Cx_SDA before I2Cx_SCL high
ns
Fast Mode
100
Standard Mode
0
7
th(SDA-SCLL)
Hold time, I2Cx_SDA after I2Cx_SCL low
µs
Fast Mode
0
0.9
Standard Mode
4.7
8
tw(SDAH)
Pulse duration, I2Cx_SDA high
µs
Fast Mode
1.3
Standard Mode
1000
9
tr(SDA)
Rise time, I2Cx_SDA
ns
Fast Mode
20 + 0.1Cb
300
Standard Mode
1000
10
tr(SCL)
Rise time, I2Cx_SCL
ns
Fast Mode
20 + 0.1Cb
300
Standard Mode
300
11
tf(SDA)
Fall time, I2Cx_SDA
ns
Fast Mode
20 + 0.1Cb
300
Standard Mode
300
12
tf(SCL)
Fall time, I2Cx_SCL
ns
Fast Mode
20 + 0.1Cb
300
Standard Mode
4
Setup time, I2Cx_SCL high before I2Cx_SDA
13
tsu(SCLH-SDAH)
µs
high
Fast Mode
0.6
Standard Mode
N/A
14
tw(SP)
Pulse duration, spike (must be suppressed)
ns
Fast Mode
0
50
Standard Mode
400
15
Cb
Capacitive load for each bus line
pF
Fast Mode
400
Table 4-37. I2C Switching Characteristics(1)
NO.
PARAMETER
MIN
MAX
UNIT
Standard Mode
10
16
tc(SCL)
Cycle time, I2Cx_SCL
µs
Fast Mode
2.5
Standard Mode
4.7
Setup time, I2Cx_SCL high before I2Cx_SDA
17
tsu(SCLH-SDAL)
µs
low
Fast Mode
0.6
Standard Mode
4
18
th(SDAL-SCLL)
Hold time, I2Cx_SCL low after I2Cx_SDA low
µs
Fast Mode
0.6
(1)
I2C must be configured correctly to meet the timings in Table 4-37.
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Peripheral and Electrical Specifications
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